Yuichiro Morita

A triple redundant controller which adopts the time-sharing fault recovery method and its application to a power converter controller

A novel fault recovery method, in which memory copy from a normal system to a fault detected system is executed in time-sharing fashion, has been implemented in a triple redundant controller. This method reduces data copy bandwidth required for recovery of the fault detected system, and allows non-stop fault recovery with only a little hardware overhead, even when the controller contains multiple processors and operates at a very short operating period. The developed controller contains triplicated processing units, each of which consists of seven 60 MIPS processor boards connected by a 30 MHz 4 byte bus. One processor board contains a bus arbiter, and each of the remaining six processor boards contains three sets of 100 Mbps two-way optical links, which can be utilized for inter-system memory copy as well as for connecting to 10 units. This controller has been applied to a power converter controller, and a 104 microsecond operating period was achieved.

Cost-Effective and Fault Tolerant Vehicle Control Architecture for X-by-Wire Systems (Part 2: Implementation Design)

X-by-Wire systems are expected to enhance vehicle driving performance and safety. This paper describes an electronic platform architecture for X-by-Wire systems that satisfies both cost-effectiveness and dependability. In the first part of this paper (Part 1), we have proposed a new electronic architecture based on a concept of autonomous decentralized systems. In the latter part (Part 2), the proposed architecture implementation to the actual vehicle control systems will be discussed. We clarify that, due to system level redundancy the proposed architecture provides, vehicle control systems can basically consist of low cost fail-silent nodes. Furthermore, for cost optimization, considering a tradeoff between hardware cost and fault detection coverage, we design a suitable hardware architecture for each node according to node function.

A one chip super graphics CPU with direct unified memory controller suitable for car information and control system

A one chip super graphics CPU with graphics and unified memory controller has been developed. It requires no dedicated graphics memory and has significantly lower system cost with 1.6 times higher performance than CPUs with state-of-the-art technology. Its process and package are 0.18 /spl mu/m and 256 pin QFP, respectively.

A realization of arbitrary BPC permutations in bidirectional hypercube and chordal ring networks

A multiple instruction stream-multiple data stream (MIMD) computer is a parallel computer with a large number of identical processing elements. The essential feature that distinguishes each MIMD computer family is the interconnection network. In this paper, we are concerned with two representative types of interconnection networks that are called the hypercube and the chordal ring networks. A family of regular graphs is presented as a possible candidate for the implementation of a distributed system and for fault-tolerant architecture. The symmetry of these graphs makes it possible to determine message routing by using a simple distributed algorithm. Arbitrary data permutations are generally accomplished by sorting. For certain classes of permutations, however, (for example, many frequently used permutations in parallel processing, such as bit reversal, bit shuffle, bit complement, matrix transpose, butterfly permutations in FFT algorithms, and segment shuffles), there are algorithms that are more efficient than the best sorting algorithm. One of these is the bit permute complement (BPC) class of permutations. We have developed algorithms for bidirectional networks. The developed algorithm in hypercube networks requires only 1 token memory register in each node. The algorithm takes the same number of steps as the maximum Hamming distance. Therefore, we have concluded that the presented algorithm is the optimal one. On the other hand, the developed algorithm in chordal ring networks requires 2 token storage register. The number of required routing steps in two kinds of networks is evaluated.