Krishna Sekar

Using a soft core in a SoC design: experiences with picoJava

Through our experience in synthesis, validation, test, and integration of the picoJava processor core in a system-on-chip (SoC) design we point out the challenges faced and issues to address in efficient reuse of a soft core.

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

In this paper, we describe FLEXBUS, a flexible, high-performance on-chip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run-time variations in communication traffic characteristics, and efficiently adapt the topology of the communication architecture, both at the system-level, through dynamic bridge by-pass, as well as at the component-level, using component re-mapping. We describe the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic. The techniques underlying FLEXBUS can be used in the context of a variety of on-chip communication architectures. In particular, we demonstrate its application to AMBA AHB, a popular commercial on-chip bus. Detailed experiments conducted on the FLEXBUS architecture using a commercial design flow, and its application to an IEEE 802.11 MAC processor design, demonstrate that it can provide significant performance gains as compared to conventional architectures (up to 31.5% in our experiments), with negligible hardware overhead.

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.The techniques underlying Flexbus are general, and are applicable to a variety of bus standards. We have implemented Flexbus as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied Flexbus to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that Flexbus provides gains of up to 34.55 % in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.

LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.

Embedded hardware and software self-testing methodologies for processor cores

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

Dynamic Platform Management for Configurable Platform-Based System-on-Chips

General-purpose System-on-Chip platforms consistingof configurable components are emerging as an attractivealternative to traditional, customized solutions (e.g., ASICs,custom SoCs), owing to their flexibility, time-to-market advantage,and low engineering costs. However, the adoptionof such platforms in many high-volume markets (e.g, wirelesshandhelds) is limited by concerns about their performance andenergy-efficiency. This paper addresses the problemof enablingthe use of configurable platforms in domains where custom approacheshave traditionally been used. We introduce DynamicPlatform Management, a methodology for customizing a configurablegeneral-purpose platform at run-time, to help bridgethe performance and energy efficiency gap with custom approaches.The proposed technique uses a software layer that detectstime-varying processing requirements imposed by a set ofapplications, and dynamically optimizes architectural parametersand platform components. Dynamic platform managementenables superior application performance, more efficient utilizationof platform resources, and improved energy efficiency,as compared to a statically optimized platform, without requiringany modifications to the underlying hardware.We illustrate dynamic platform management by applying itto the design of a dual-access UMTS/WLANsecurity processingsystem, implemented on a general-purpose configurable platform.Experiments demonstrate that, compared to a staticallyoptimized design (on the same platform), the proposed techniquesenable upto 33% improvements in security processingthroughput, while achieving 59% savings in energy consumption(on average).

Configurable platforms with dynamic platform management: an efficient alternative to application-specific system-on-chips

Emerging trends in system design indicate that in the future, a large role will be played by System-on-Chip (SoC) platforms consisting of general-purpose, configurable components. Commercially available SoC platforms provide some degrees of configurability, most of which are limited to one-time (static) customization of platform hardware. However, with increasing application diversity, time-varying requirements, and the convergence of multiple applications on the same platform, there is a growing need for SoC platforms that can be dynamically configured in order to adapt to changing requirements. In this paper, we propose general-purpose, dynamically configurable, SoC platforms featuring multiple configurability options, and illustrate their advantages over existing design styles. We survey technologies that aim at providing dynamically configurable platform components (e.g., processors, caches, memory sub-systems, bus architectures), and associated techniques for exploiting such configurability. In particular, we illustrate how run-time platform customization of configurable, general-purpose platforms using Dynamic Platform Management techniques (using a dual-access UMTS/WLAN security processing system as a case study) can achieve significant improvements in overall system performance and energy-efficiency.

Design for Verification at the Register Transfer Level

In this paper we introduce a novel concept that can be used for augmenting simulation based verification at the Register Transfer Level (RTL). In this technique the designer of an RTL circuit introduces some well understood extra behavior (through some extra circuitry) into the circuit under verification. This can be termed as design for verification. During RTL simulation this extra behavior is utilized in conjunction with the original behavior to exercise the design more thoroughly thus making it easier to detect errors in the original design. Once the circuit is thoroughly verified for functionality the extra behavioral constructs can be removed to produce the original verified design. Extensive experiments on a number of industrial circuits demonstrate that the method is promising.

Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms

Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on system-on-chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC platforms that are capable of providing high performance in the face of such variations. Recent advances in circuits and architectures are enabling platforms that contain various mechanisms for runtime adaptation. However, the problem of exploiting such configurability in a coordinated manner at the system level remains a challenging task. In this work, we focus on two configurable subsystems of SoC platforms that play a crucial role in determining overall system performance, namely, the on-chip communication architecture, and the on-chip memory architecture. Using detailed case studies, we demonstrate the limitations of designs in which the architectural configuration of a bus-based communication architecture and the placement of data in memory are statically optimized, and those in which each is customized separately, without considering their interdependence. We propose an integrated methodology for dynamically relocating on-chip data and reconfiguring the communication architecture, and discuss the necessary hardware support. Experiments conducted on an SoC platform that integrates decoders for the UMTS (3G) and IEEE 802.11a (wireless LAN) standards demonstrate that the proposed integrated adaptation technique helps boost the maximum achievable performance by up to 32% over the best statically optimized design