Ku-Feng Yang

Production Worthy 3D Interconnect Technology

A three dimensional integrated circuit (3DIC) integration flow, process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity and resulted in good electrical performance. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. By wafer level electrical testing, yielding 20K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated.