Tsang-Jiuh Wu

High-aspect ratio through silicon via (TSV) technology

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

An ultra-thin interposer utilizing 3D TSV technology

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL

A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8μm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated from good continuity of long RDL chains. Two layers of backside RDL are used to redistribute the IO from TSV at 0.2 mm pitch to BGA at 0.6 mm pitch. With the same multi-die integration capability as in CoWoS™, the CoW package has additional advantages of lower z-height, better thermal dissipation, and lower cost. Moreover, mechanical and thermal simulations reveal a relatively greater life cycle endurance for temperature cycling on board (TCoB) test. The CoW package passed preliminary component-level reliability assessments including μHAST, HTS and TC. This provides a promising CoWoS™ alternative for lower cost and thinner package with improved thermal performance. It also possesses the flexibility to combine with fan-out technology to be fitted in applications requiring higher IO count or larger BGA pitch.