Kuba Raczkowski

A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS

For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandwidth for the AV-OFDM mode. For the single-carrier modes, the ECMA 387 standard [2] foresees the possibility of bonding together adjacent channels, yielding higher data-rates. Radios for these 60GHz standards often use phased antenna arrays to relax the link budget. A phased-array receiver needs a variable phase shift on each antenna path and a combiner that sums the signals from the individual paths after phase shifting. The beamforming circuitry presented here handles 4 paths. It can operate both with one 0.88GHz channel and with bonding of two such channels. Phase shifts are realized with a resolution better than 20°. Bandwidth is high thanks to the use of current amplifiers with very low input impedance.

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

This paper presents a 10-bit, 550-fs step Digital-to-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are below 1.8 LSB and 0.8 LSB, respectively. The DTC phase noise floor is below -154 dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At 10 GHz output, the in-band phase noise of the PLL with the DTC embedded is -105 dBc/Hz. The PLL achieves 270 fs RMS jitter, consuming 26 mW.

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8-63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to -94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below -40 dBc.

A 42mW wideband baseband receiver section with beamforming functionality for 60GHz applications in 40nm low-power CMOS

A 4-antenna path beamforming analog baseband section implemented in 40 nm low power CMOS for use in a phased-array 60 GHz receiver is presented. The circuit combines fourth-order filtering with a cutoff frequency of 1 GHz, beamforming and variable gain between 10.6 dB and 30 dB. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for QAM16 modulation according to IEEE 802.15.3c. The circuit consumes less than 42 mW.

A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter

This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.

A four-path 60GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90nm CMOS

We present a 60 GHz four-antenna phased-array direct conversion receiver in 90 nm RF CMOS with an LO based on subharmonic injection locking, beamforming that is partially in the LO path and partially at analog baseband, and an analog baseband section. The LO system features a set of four 60 GHz oscillators, locked to the fifth harmonic of a central oscillator, improving the phase noise performance and robustness. Phase shifting is realized in two steps and two domains, which reduces the complexity of phase shifters and signal degradation at analog baseband. Signal combination is performed at analog baseband, followed by a variable-gain amplifier and a baseband filter, which together allow for 6-th order filtering with 880 MHz bandwidth and 20 dB of gain adjustment with 1 dB steps. The system provides a maximum conversion gain of 42 dB with a total power consumption of 450 mW and chip area of 3.15 × 1.9 mm.

A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers

This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the top-level chip floorplan. It is shown that the proposed structure does not introduce extra power consumption compared to the conventional approach, while obtaining a higher SNR. A four-antenna-path version of the proposed topology is implemented in 40 nm low-power CMOS as a prototype together with a variable gain block forming a complete analog baseband section for a phased-array receiver. The functionality includes beamforming with a resolution better than 6.8 degrees, fourth-order lowpass filtering with a 1 GHz cutoff frequency, variable gain between 10.6 and 30 dB and automatic DC offset compensation. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for 16-QAM modulation according to IEEE 802.11ad. The circuit consumes between 30 and 42 mW.