Jonathan Borremans

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

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A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

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Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 mm2 and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

In this paper, a CMOS implementation of phased-array receiver front-end, based on a widely tunable QVCO is presented. Each path achieves 30dB of gain and a minimum NF of 7.1dB, yielding a system NF of 4.1dB. The overall current draw is 54mA from a 1.2V supply. Additionally, a calibration procedure to mitigate the analog impairments imposed by the proposed implementation is demonstrated.

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS

A 5 mm2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.

A 2.4 GHz Low-Power Sixth-Order RF Bandpass

A 50times35mum2 DC-to-6GHz LNA is designed in a digital 90nm CMOS process. It draws 8.1 mA from a 1.2V supply and achieves a minimum NF of 2.8dB and 17dB of gain. In the 6GHz bandwidth, S11 is below -10dB and the IIP3 varies between -16 and -7dBm. ESD protection of 3.2kV HBM is implemented, as well as an optional second stage with gain selection adding up to 4dB of gain

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As CMOS scales down and grows more expensive, area-aware RF front-end design becomes appropriate. A wideband front-end is presented that uses an inductorless LNA and downconversion section up to 6 GHz. Frequency synthesis is realized using a single-inductor dual-band 3.5 and -10 GHz VCO. In-depth analysis describes the operation of the 4-port oscillator, and compares phase noise to that of a classical VCO. The front-end is realized in 90 nm digital CMOS. The LNA achieves a noise figure of 2.7 dB with an average IIP3 of -2 dBm. The dual-band VCO achieves a phase noise of -122 dBc/Hz and -128 dBc/Hz at 3.9 GHz and 10 GHz, respectively, at 2.5 MHz offset. Both circuits are embedded in a wideband direct-conversion front-end consuming less than 60 mW from a 1.2 V supply.