Bertrand Parvais

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s

Obtaining sufficient EVM in all four 1.76GHz bandwidth chann1.76GHzels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex as QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels. Wireless applications often use digital low-power (LP) CMOS technology to implement single-chip transceivers. The high Vt and the thin metal interconnect layers constrain the mm-Wave circuit performance. This paper presents a digital LP 40nm CMOS 60GHz transceiver (TRX) IC that obtains an EVM better than -17dB in all 4 channels.

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8-63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to -94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below -40 dBc.

A four-path 60GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90nm CMOS

We present a 60 GHz four-antenna phased-array direct conversion receiver in 90 nm RF CMOS with an LO based on subharmonic injection locking, beamforming that is partially in the LO path and partially at analog baseband, and an analog baseband section. The LO system features a set of four 60 GHz oscillators, locked to the fifth harmonic of a central oscillator, improving the phase noise performance and robustness. Phase shifting is realized in two steps and two domains, which reduces the complexity of phase shifters and signal degradation at analog baseband. Signal combination is performed at analog baseband, followed by a variable-gain amplifier and a baseband filter, which together allow for 6-th order filtering with 880 MHz bandwidth and 20 dB of gain adjustment with 1 dB steps. The system provides a maximum conversion gain of 42 dB with a total power consumption of 450 mW and chip area of 3.15 × 1.9 mm.

A 54–69.3 GHz dual-band VCO with differential hybrid coupler for quadrature generation

This paper presents a 40nm CMOS transformer-based dual-band VCO with differential hybrid coupler for I/Q generation. The average phase noise of the combination over the 54 to 69.3GHz tuning range is -90dBc/Hz at 1MHz offset while the best FOM value is 177dB. Along the wide tuning range from 54 to 67GHz, the I/Q mismatch of the hybrid coupler is less than 3°. The area of the hybrid is only 60μm-65μm.

A mm-wave 40 nm CMOS subharmonically injection-locked QVCO with lock detection

This paper demonstrates a 40 nm CMOS mm-wave subharmonically injection-locked QVCO with a lock detection mechanism. The locking range is more than 2GHz over the 55-63 GHz tuning range. An envelope detector simplifies the calibration of the QVCO. In addition, the lock detector, based on passive mixing, detects the lock condition simply by a change in the DC operating point. The large locking range, the large tunability and the combination of envelope detector and lock detector offer a simple approach for robust mm-wave frequency synthesis based on subharmonic injection locking.

Design and Tuning of Coupled-LC mm-Wave Subharmonically Injection-Locked Oscillators

This paper analyzes and demonstrates the use of coupled-LC tanks to enlarge the locking range (LR) of millimeter-wave (mm-wave) subharmonically injection-locked oscillators. Design guidelines are derived from a simplified analysis. Different techniques are proposed to tune the coupled-LC tank. A mm-wave subharmonically injection-locked quadrature voltage-controlled oscillator in 40-nm CMOS verifies the proposed approach. The LR is larger than 2 GHz over a 55-63-GHz tuning range. An on-chip envelope detector facilitates the tuning of the coupled-LC tank. The phase noise and the quadrature-phase imbalance are uniform over almost the whole LR.

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.