Chun-Lin Ko

A 2.4–5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier

A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 mum CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.

A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multistandard Wireless Receiver

A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500 MHz 3 dB-bandwidth. Switching transistor is used to provide variable gain control over a 12 dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11 b/g and part of 802.11a. Fabricated in 0.13 um CMOS process the LNA achieves up to 25 dB power gain, 2.2 dB noise figure, -1 dBm IIP3 while consuming less than 5 mW from 1-V power supply.

On-Chip Transmission Line Modeling and Applications to Millimeter-Wave Circuit Design in 0.13um CMOS Technology

This paper presents the on-chip transmission line modeling and applications to circuit design at millimeter-wave (ram-wave) frequencies. The microstrip model of circuit simulators benefits in fast calculations of the characteristics of microstrip lines. As the structure of on-chip microstrip differs from the modeled structure, two key parameters of the microstrip model need to be modified for the different electromagnetic (EM) behavior according to the measured microstrip line. With proper parameters, the traditional transmission line model is able to accurately predict the real characteristic of on-chip microstrip lines without time-consuming EM simulation. A mm-wave microstrip line filter and a single-stage cascode low noise amplifier (LNA) are fabricated to verify the model. All passive components for input/output matching networks and bias networks are on-chip. The LNA takes the supply voltage and dc current of 1.4 V and 10 mA, respectively. A gain of 3.8 dB and an input/output return loss of 8.5/7.0 dB are measured at 60.3 GHz. The simulation results in both circuits are in good agreement with measured data.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as -11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal-oxide-semiconductor technology. The measured voltage conversion gain is -1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm2.

2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

A complementary metal oxide semiconductor (CMOS) power amplifier (PA) using a wafer-level bondwire spiral inductor with high-quality factor (Q) is presented. The inductor is made by three top metal traces connected with bondwire loops above the CMOS chip. The proposed inductor with 2.75-nH inductance achieves a Q of 18, which is three times as much as that of a conventional CMOS standard spiral inductor at 2.4 GHz. The Q of the inductor is over 15 from 2 to 14 GHz, which can cover the frequency band of wireless sensor network and worldwide interoperability for microwave access applications. The output power and power-added efficiency of the PA with the inductor are improved by 1.5 dBm and 7% as compared with those of the fully integrated CMOS PA, respectively.

A CMOS WLAN/GPRS dual-mode RF front-end receiver

A dual-mode, triband RF front-end receiver for GSM-900, DCS-1800 and IEEE 802.11b/g is introduced. With advanced architecture selection and frequency plan, only a single VCO and frequency synthesizer are required for both GSM/GPRS cellular and IEEE 802.11b/g WLAN. The receiver front-end has been realized in a 0.25 /spl mu/m CMOS process. It dissipates about 30 mA from a 2.7 V supply for all modes and exhibits noise figures of 3 dB for the GSM-900 band, 5.9 dB for the DCS-1800 band, and 5.7 dB for 2.4 GHz WLAN.

A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines

A V-band low noise amplifier has been demonstrated in 90 nm CMOS. The LNA design was used the low loss microstrip lines for all matching networks. To fulfill the metal density requirement in fabrication, the ground plane needs slots. The direction of the slot pattern affects the line loss over 30% at 60 GHz, according to the analysis and experimental results. By slot filling under the line, the line loss can be improved 10% further. The topology of LNA is 3 stage common-source cascades for low supply voltage limited by process. Using the microstrip lines, the LNA exhibited a low noise figure of 5.6 dB and a gain of 10.8 dB at 60 GHz with only 5.5 mW from a 1.0 V power supply.

A low-cost broadband bondwire interconnect for THz heterogeneous system integration

A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.

A CMOS dual-mode RF front-end receiver for GSM and WCDMA

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented. Because the system concepts of GSM and WCDMA are totally different from the standards, the chip uses low-IF and zero-IF receiver architecture for GSM and WCDMA, respectively. This chip consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end has been implemented in a standard 0.25/spl mu/m CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3dB, 36dB for the GSM900, 5.9dB, 31dB for the DCS1800, and ?-dB, 17.2dB for the WCDMA, respectively.