Kumar Nagarajan

Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA

TSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip. Furthermore, for an interposer that does not contain any active device, already established process technology could be applied, TSV pitch could be coarser and a thicker interposer could be used. This paper presents the development of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mm×42.5mm substrate through 180um pitch C4 bumps. TSV fabrication process steps and assembly process of the large logic die mounted on the TSV interposer with lead-free micro-bumps have been optimized as well as assembly of the component on the organic substrate. 3D thermal-mechanical modeling and simulation for the packaged device with TSV interposer have been performed. The samples have been subjected to thermal cycling, electro-migration and moisture sensitivity tests. Effect of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated. Several DOEs have been performed to optimize design and material selection in order to maximize yield and reliability. Finally, Si interposer seemed to be a low-risk 3D path to have a reliable package with acceptable warpage/coplanarity, passing 1000TCB without any crack, delamination or void being detected in low-k, TSV, micro bumps and C4 bumps.

Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

For the last few decades semiconductor industry has been following Moore Law effectively, which has resulted in significant miniaturization of transistors and on chip logic circuitry. Below the 28nm node, as design complexity of the IC (Integrated Circuits) increases, cost and risk associated with these designs are becoming prohibitive for many companies. Three dimensions (3D) die stacking methodology offers unique advantages of low power and high bandwidth per watt without increasing the cost significantly. For FPGAs (Field Programmable Gate Array), stacked silicon integration (SSI) technology offers a cost effective solution to build large die with very high logic cell count. In order to create a larger FPGA, four different 28nm FPGA die are connected to each other through a 65nm passive silicon interposer. The FPGA die are connected to interposer through micro-bumps (ubumps). This paper describes the technical challenges associated with 3D integration of 100um thin interposer and FPGA die on to a package and stacked die package reliability. The assembly test vehicle was comprised of four 28nm chips mounted side by side on a 25 mm × 31 mm 100um thick interposer with thousands of micro-bumps at 45um pitch. This top die and interposer stack was assembled on a 35mm × 35mm and 45mm × 45mm package with 180um pitch C4 bumps. Several assembly experiments were performed to compare performance of mass reflow assembly and thermo compression bonding assembly to join top FPGA die with ubumps. Assembly yield and reliability were used as two main criteria in deciding the best assembly process. Micro-bump resistance was monitored by Through Silicon Via (TSV) chains, Kelvin bump structure and daisy chains in order to check interconnect integrity after assembly and during reliability testing. After assembly evaluations, separate underfill screening design of experiment (DOE) was performed to choose the best underfill candidates for reliability evaluations. Reliability evaluations were performed with best underfill candidates and parts were subjected to L4 preconditioning and -55°C to 125°C thermal cycling. Parts were subjected to extended thermal cycling, i.e. beyond 1000 cycles, to understand the other possible failure modes. Assembly evaluations showed that the choice of the assembly process was strongly dependent on the die size, interposer design and interposer process. Choice of flux also affected the ubump assembly yield and underfill flow. Underfilling experiments confirmed that optimization of underfill process required optimization of dispense pattern, ubump parameters. Reliability evaluations showed that the reliability was affected by choice of underfill, interposer cleaning, and die thickness/package structure. One of the common failure modes was delamination between interposer and C4 underfill.

Assembly process integration challenges and reliability assessment of multiple 28nm FPGAs assembled on a Large 65nm passive interposer

Stacked die packaging has been gaining traction in recent years due to cost and manufacturing issues associated transistor scaling. 3D die stacking architecture with through silicon vias offers a unique combination of low power and high bandwidth per watt without increasing the cost significantly. For Xilinxs FPGAs (Field Programmable Gate Array), due to its repetitive and unique structures, Stacked Silicon Integration (SSI) technology becomes a perfect fit to provide a cost effective solution to build large programmable logic devices with very high logic cell count. In the current configuration, four separate 28nm FPGA die were connected to each other through a 65nm passive silicon interposer. Arrays of more than 10k micro-bumps (ubumps) stitched these four dies together through the silicon interposer. This paper describes the technical and reliability challenges associated with 3D integration of 100um thin interposer and FPGA die on to a single package.

Microvia reliability improvement for high density interconnect substrate

High density interconnect (HDI) flip-chip ball grid arrays (FCBGA) substrate becoming more and more popular for high end applications, to meet greater number of I/O pads, increasing I/O pad density, higher operational frequencies and smaller package body size. Microvia in HDI substrate has much smaller scale comparing to conventional plated through-hole (PTH) substrate, which is prone to have microvia crack under thermal mechanical loading. This study shows that additional etching on via interface could improve microvia integrity.

Missing ball improvement for different lead free solders

Government regulations for handling electronic waste materials are becoming more stringent. The European Union (EU) and China implemented regulations on the restriction of use of hazardous substances (RoHS) for electrical and electronic equipment on 1 July 2006 and 1 March 2007 respectively. One of the many intentions of these regulations is to ban the use of lead (Pb), which is commonly used for BGA solder ball. BGA solder ball composition need be changed from eutectic solder (Sn63Pb37) to SnAgCu or SnAg lead free solders, because of above environmental and regulation reasons [1,2]. Since the introduction of Pb-Free initiatives, both academic and industry have extensively investigated solder ball composition [3,4,5] and proposed to use SAC305/405 solder alloys because of its higher strength and reasonable melting point. However, on volume production, the industry realized these alloys are more fragile, and susceptible to high ppm level of IMC fracture under high-strain rate, e.g. handling, shipping, socketing etc.