Kunal Datta

Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers

Design equations and performance limits of Class-E power amplifiers at mm-waves, including the limitations imposed by active and passive devices in a given technology, are presented in this paper. A beyond nominal breakdown voltage Class-E design methodology for SiGe HBT power amplifiers is proposed to generate high output power while maintaining high Class-E efficiency. A mm-wave SiGe stacked Class-E architecture is also introduced to increase the overall voltage swing, with each series stacked device operating in the beyond nominal breakdown mode. The mm-wave beyond BVCEO operation of SiGe HBTs has been demonstrated experimentally in an integrated 45 GHz Class-E power amplifier fabricated in a 0.13 μm SiGe BiCMOS process with 20 dBm measured output power at 31.5% peak power-added efficiency (PAE). The series stacking of mm-wave Class-E power amplifier concept is also verified by fabricating double-stacked and triple-stacked SiGe HBT power amplifiers in 0.13 μm SiGe BiCMOS process which demonstrate a measured output power of 23.4 dBm at 41 GHz with peak PAE of 34.9%. High power, highly efficient, switching power amplifier unit cells presented in this paper can facilitate realization of efficient Watt-level mm-wave digital polar transmitters.

Analysis, design and implementation of mm-Wave SiGe stacked Class-E power amplifiers

Design equations and performance limits of stacked Class-E power amplifiers at mm-waves, including the limitations imposed by device parasitics, are presented in this paper. As a proof of concept of this parasitic aware mm-wave Class-E design methodology and to demonstrate the beyond BVCEO Class-E operation in a stacked architecture at mm-wave frequencies, a Q-band, single ended, two-stage, double-stacked, Class-E power amplifier is designed in a 0.13 μm SiGe HBT BiCMOS process. The measured performance of the fabricated chip show 23.4 dBm maximum output power at 34.9% peak power added efficiency (PAE), and 14.6 dB of power gain across 5 GHz centered around 41 GHz for a supply voltage of 4 V. The total chip area including the pads is 0.8 mm × 1.28 mm.

A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE

A Q-band two-stage Class-E power amplifier is designed and fabricated in a 0.13 μm SiGe HBT BiCMOS process. A mm-wave Class-E architecture considering the effect of various interconnect parasitics is adopted to achieve high power efficiency. Proper input and output networks have been designed to enable efficient switching of the HBT at large voltage swings without causing unwanted impact ionization-induced negative base current and instability. The measured performance of the fabricated chip show 20.2 dBm maximum output power, 31.5% peak power added efficiency, and 10.5 dB power gain across 4 GHz centered around 45 GHz for a supply voltage of 2.5 V. The total chip area including the pads is 0.74 mm × 1.7 mm.

A triple-stacked Class-E mm-wave SiGe HBT power amplifier

A Q-band, single ended, two-stage, triple-stacked, Class-E power amplifier is designed and fabricated in a 0.13 μm SiGe HBT BiCMOS process. The Class-E amplifier comprises of three series-stacked HBTs with capacitive divider networks at the HBT bases and collectors to ensure proper large signal swing and beyond BVCEO operation at mm-wave frequencies. The measured performance of the fabricated chip show 22.2 dBm maximum output power at 20.8% peak power added efficiency, and 15.4 dB of power gain across 4 GHz centered around 40 GHz for a supply voltage of 6.5 V. The total chip area including the pads is 0.8 mm × 1.28 mm.

A 22.4 dBm Two-Way Wilkinson Power-Combined Q-Band SiGe Class-E Power Amplifier with 23% Peak PAE

A Q-band two-stage Class-E power amplifier is designed and fabricated in a 0.13 μm SiGe HBT BiCMOS process. A low-loss wide-band two-way Wilkinson power combiner is used for on-chip power dividing and combining at the input and output of the design. A mm-wave layout-aware class-E design procedure has been followed to enable efficient switching mode operation of the power amplifier in the Q-band. Stabilization networks and subharmonic terminations have been included to prevent the occurrence of unwanted impact ionization-induced negative base current and even/odd mode oscillation in the power-combined design. The fabricated chip shows a measured performance of 22.4 dBm output power at 23% peak power added efficiency (PAE), and 9 dB power gain across 4 GHz centered around 45 GHz for a supply voltage of 2.5 V. The total chip area including the pads is 1.1 mm × 2.2 mm.

75 – 105 GHz switching power amplifiers using high-breakdown, high-fmax multi-port stacked transistor topologies

High-breakdown, high-fmax multi-port transistor topologies are presented in this work for realizing high power, highly efficient mm-wave switching power amplifiers at 75-105 GHz. Implemented in a 90nm SiGe BiCMOS process, the proposed active structures comprising of two and three stacked transistors with integrated layout parasitics achieve (fmax, breakdown voltage) of (295 GHz, 8V) and (260 GHz, 11 V) respectively and demonstrate peak (output power, PAE) of (22 dBm, 19%) at 85 GHz and (23.3 dBm, 17%) at 83 GHz respectively. The implemented designs are benchmarked against a 88 GHz 19.5 dBm, 16% PAE W-band Class-E power amplifier using native transistor footprints fabricated in the same 90nm SiGe BiCMOS process. The superior performance of the composite transistor designs highlight the benefit of the proposed approach.

Waveform engineering in a mm-Wave stacked-HBT switching power amplifier

A new family of hybrid stacked power amplifiers (named as ‘Class-K’) are presented where each of the series stacked transistors can operate independently as different class of switching amplifiers. The voltage and current waveforms of the stacked transistors are shaped by independent harmonic load networks connected to the collector nodes of each of the stacked HBTs. A properly-designed Class-K amplifier can simultaneously achieve the high efficiency of Class-E/F amplifiers, high output power of Class-EF amplifiers, and high power gain of Class-E amplifiers. A proof-of-concept two-stage two-stacked balanced Class-K amplifier implemented in a 0.18 µm SiGe HBT BiCMOS process demonstrates 25.5 dBm output power and 26% peak PAE at 34 GHz.

A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS

This paper presents a 60 GHz class-E digital power amplifier (DPA) that generates energy-efficient, non-constant envelope modulations up to 25 Gb/s. The DPA achieves a peak drain efficiency of 17.7% at a Vsat of 7.4 dBm. By means of direct digital amplitude modulation of the 6-bit output stage, the DPA produces error-free, high-order constellations (16-QAM, 32-QAM, 64-QAM) up to 5 GSym/s with error vector magnitudes (EVMs) <-26 dB. Compared to prior 60 GHz DPAs, >3.5X higher data rates at comparable average efficiencies is achieved.

Switch-mode mm-wave silicon power amplifiers

Introduction to switching power amplifiers Switch-mode power amplifiers (PAs) are motivated by the insight that power-amplifier efficiency is maximized by minimizing the amount of overlap between device current and device voltage. In other words, it is desirable to minimize the amount of time spent by the device supporting a non-zero current and non-zero voltage simultaneously. Switch-mode power amplifiers accomplish this by employing the active device as a switch that transitions between two states – an ON state, where the resistance of the device is ideally zero and in practice small compared with the other impedances in the circuit, and an OFF state, where the resistance of the device is ideally infinite and in practice high compared with the other circuit impedances. Consequently, the active device forces the current and voltage waveforms to be non-overlapping – during the ON state, the switch supports non-zero current but the voltage across it is close to zero, and during the OFF state, the switch supports non-zero voltage but the current through it is zero. Under idealized conditions, 100% efficiency can be achieved assuming switching losses are eliminated. This typically requires the voltage across the switch to be shaped to zero at the end of the OFF state as the switch is turning ON, so that the switch is not turned ON with non-zero charge stored on its output capacitance. Assuming such a “zero-voltage switching” (ZVS) condition is met, 100% efficiency can be achieved, unlike for current-source-based power amplifiers, where 100% efficiency can be achieved only in class-C operation as the output power approaches zero or by using class-F tuning, where 100% efficiency is achieved asymptotically with infinite harmonic tuning. In practice, however, the efficiency is limited by parasitic effects, such as conduction loss in the non-zero switch resistance and loss in the passive output matching network. Switch-mode power amplifiers are distinct from their current-source counterparts (Fig. 5.1) in that they are (at least partially) voltage-forcing amplifiers. During the ON portion of the RF cycle, the device voltage is forced to ground through the switch, and during the OFF portion, the voltage is determined either by the load network or perhaps by the presence of a complementary switch (as is the case in inverter-like class-D power amplifiers).