Anandaroop Chakrabarti

High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS

Stacking devices in CMOS power amplifiers (PAs) increases the achievable output voltage swing, thereby increasing the output power and efficiency, particularly at millimeter-wave frequencies. This work presents stacked CMOS PAs based on an improved Class-E design methodology, where device loss is explicitly accounted for in the analysis and design procedure. Design guidelines and fundamental limits on achievable performance are presented. Two fully-integrated 45GHz prototypes with 2 and 4 stacked devices have been fabricated in IBMs 45nm SOI CMOS technology. Measurement results yield a peak PAE of 34.6% for the 2-stacked PA with a saturated output power of 17.6 dBm, and a peak PAE of 19.4% for the 4-stacked PA with a saturated output power of 20.3 dBm. The former represents the highest PAE reported for CMOS mmWave PAs, and the latter represents the highest output power achieved from a CMOS mmWave PA. The paper also describes the modeling of active and passive devices for mmWave CMOS PAs for good model-hardware correlation.

Low-Noise Active Cancellation of Transmitter Leakage and Transmitter Noise in Broadband Wireless Receivers for FDD/Co-Existence

A technique for active cancellation of transmitter self-interference in wideband receivers is presented. The active TX leakage cancellation circuitry is embedded within a noise-cancelling low-noise transconductance amplifier (LNTA) so that the noise and the distortion of the cancellation circuitry are cancelled, resulting in a noise-cancelling, self-interference cancelling receiver (NC-SIC RX). A second-point cancellation of TX noise in the RX band is performed after the LNTA so that the noise impact of the second canceller is reduced. Theoretical analyses related to the benefits and limits of active self-interference cancellation as well as the simultaneous cancellation of the noise and distortion of the cancellation circuitry are presented. A 0.3-1.7 GHz receiver with the proposed active cancellation is implemented in 65 nm CMOS. The proposed scheme can cancel up to +2 dBm peak TX leakage at the receiver input. The triple beat at +2 dBm peak TX leakage is 68 dB and the effective IIP3 is +33 dBm, representing increases of 38 and 19 dB, respectively, over the receiver without cancellation. The associated increase in receiver NF is less than 0.8 dB. In addition, the scheme effectively suppresses TX noise in RX band by up to 13 dB. The technique can be more generally viewed as an active combining structure that has ideally no noise penalty and is able to handle large signals without generating distortion and can be applied to any scenario where a replica of an interference signal can be generated.

High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation

Series stacking of multiple devices is a promising technique that can help overcome some of the fundamental limitations of CMOS technology in order to improve the output power and efficiency of CMOS power amplifiers (PAs), particularly at millimeter-wave (mmWave) frequencies. This paper investigates the concept of device stacking in the context of the Class-E family of nonlinear switching PAs at mmWave frequencies. Fundamental limits on achievable performance of a stacked configuration are presented along with design guidelines for a practical implementation. In order to demonstrate the utility of stacking, three prototypes have been implemented: two fully integrated 45-GHz single-ended Class-E-like PAs with two- and four-stacked devices in IBMs 45-nm silicon-on-insulator (SOI) CMOS technology, and a 45-GHz differential Class-E-like PA with two devices stacked in IBMs 65-nm low-power CMOS process. Measurement results yield a peak power-added efficiency (PAE) of 34.6% for the two-stacked 45-nm SOI CMOS PA with a saturated output power of 17.6 dBm. The measurement results also indicate true Class-E-like switching PA behavior. A peak PAE of 19.4% is measured for the four-stacked PA with a saturated output power of 20.3 dBm. The two-stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOS mmWave PA including those that employ power combining. The 65-nm CMOS differential two-stacked PA exhibits a peak PAE of 28.3% with a saturated differential output power of 18.2 dBm, despite the poor ON-resistance of the 65-nm low-power nMOS devices. This paper also describes the modeling of active devices for mmWave CMOS PAs for good model-hardware correlation.

Large-scale power-combining and linearization in watt-class mmWave CMOS power amplifiers

Switching-class PAs employing device-stacking have been recently explored to meet the challenge of efficient power amplification at mmWave frequencies at moderate power levels of around 20dBm. In this paper, we propose the use of a single-step, large-scale (8-way), 75%-efficient lumped quarterwave power combiner that is co-designed with stacked Class-Elike PA unit cells to enable a Q-band 45nm SOI CMOS PA with a peak Psat of 27.2dBm (>0.5W), peak PAE of 10.7% and 1dB flatness in Psat over nearly the entire Q-band (3346GHz). This measured output power level is approximately 5 × higher than prior reported mmWave silicon PAs. In order to support complex modulations with high average-efficiency, we also propose a novel linearizing architecture that combines largescale power combining, supply-switching for efficiency under backoff and dynamic load modulation for linearization. A second fully-integrated 42.5GHz 45nm SOI CMOS PA is implemented based on this architecture and achieves 60% of the peak efficiency at 6dB back-off.

Large-Scale Power Combining and Mixed-Signal Linearizing Architectures for Watt-Class mmWave CMOS Power Amplifiers

Millimeter wave (mmWave) CMOS power amplifiers (PAs) have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear PAs with high efficiency under back-off. A novel linearizing architecture which simultaneously employs large-scale power combining, linearization through dynamic load modulation, and improved efficiency under back-off by supply-switching and load modulation is introduced. A quarter-wave combiner that exploits lumped spiral inductor equivalents of quarter-wave transmission lines with higher characteristic impedance enables one-step, low-loss, eight-way combining with a measured efficiency of 75% at 45 GHz. Eight-way combining of stacked SOI CMOS PAs results in a PA array with watt-class ( 27 dBm) saturated output power (3 × higher than prior art) and ultra-wideband operation (33-46 GHz) in 45 nm SOI CMOS. Another 45 nm SOI CMOS prototype, a three-bit digital to mmWave PA array, utilizing the proposed linearizing architecture achieves 23.3 dBm of saturated output power at 42.5 GHz, PAE -6dB /PAE peak = 67.7% as well as excellent linearity (DNL 0.5 LSB} and INL 1 LSB using end-point fit).

A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation

This paper presents a fully integrated 60 GHz directconversion transceiver in 45 nm SOI CMOS for same-channel full-duplex (FD) wireless communication. FD operation is enabled by a novel polarization-based wideband reconfigurable selfinterference cancellation (SIC) technique in the antenna domain. The antenna cancellation can be reconfigured from the IC to combat the variable SI scattering from the environment during in-field operation. A second RF cancellation path with> 30 dB gain control and> 360° phase control from the transmitter (TX) output to the LNA output further suppresses the residual SI to achieve the high levels of required SIC. With antenna and RF cancellation together, a total SI suppression of > 70 dB is achieved over a cancellation bandwidth of 1 GHz and can be maintained in the presence of nearby reflectors. In conjunction with digital SIC (DSIC) implemented in MATLAB, a FD link is demonstrated over 0.7 m with a signal-to-interference-noise-and-distortion ratio (SINDR) of 7.2 dB. To the best of our knowledge, this work achieves the highest integration level among FD transceivers irrespective of the operation frequency and demonstrates the first fully integrated mm-wave FD transceiver front-end and link.

An improved analysis and design methodology for RF Class-E power amplifiers with finite DC-feed inductance and switch On-resistance

Previous analytical efforts to incorporate the impact of finite switch ON-resistance into the design procedure of Class-E power amplifiers (PAs) have imposed one or both of the so-called “Class-E switching conditions”, namely zero voltage switching (ZVS) and zero derivative of voltage at switching (ZDVS). These are essential for high efficiency operation only in the absence of losses. In this work, more general design equations have been derived without imposition of either ZVS or ZDVS. The optimal design is found to exhibit neither ZVS nor ZDVS, thereby validating the analysis. For the first time, an attempt has been made to incorporate the input power into the analysis, which facilitates optimization of power-added efficiency (PAE). The resulting designs exhibit better performance in terms of output power and PAE compared to existing design approaches. The analytical results have been verified through Spectre-RF simulations at 5GHz in 0.18µm and 65nm CMOS. Through this design procedure, we further demonstrate that Class-E PAs at 5GHz based on thick-oxide devices in 0.18µm CMOS, despite their lower speed, outperform those based on 65nm CMOS devices due to their higher voltage-handling capability.

Dual-Output Stacked Class-EE Power Amplifiers in 45nm SOI CMOS for Q-Band Applications

Stacking multiple devices improves the output power and efficiency in mmWave power amplifiers by increasing the achievable output voltage swing. This work presents a new topology for stacked Class-E-like power amplifiers. In this technique, a Class-E load network is placed at the drain node of each stacked device, which imparts a true Class-E behavior to all the devices in the stack. The resulting topology is called the Dual (Multi) Output Stacked Class-EE PA. Two Q-band prototypes - a unit cell with 2 devices stacked, and a power-combined version employing two such unit cells - have been fabricated in IBMs 45nm SOI CMOS technology using the 56nm body-contacted devices. Measurements yield a peak PAE of 25.5% for the Dual Output Stacked Class-EE unit cell with saturated output power of 17.9 dBm, and a peak PAE >;16% for the power-combined version with saturated output power >;19.1 dBm. Excellent correspondence is observed between simulation and measurement as a consequence of active and passive device modeling efforts.

Design considerations for stacked Class-E-like mmWave high-speed power DACs in CMOS

This work describes design considerations for realizing high power mmWave DACs with high efficiency under modulation based on switching-PA DAC cells. A stacked Class-E-like SOI CMOS power amplifier is turned ON/OFF by means of digital circuitry to sustain high-speed 1-bit ASK (OOK) modulation, while high average efficiency is achieved by means of supply-switching. Factors affecting modulation speed, dynamic power dissipation, impact of digital path delays and supply/ground bounce are discussed and design guidelines are provided. A fully-integrated 47GHz prototype has been fabricated in IBMs 45nm SOI CMOS technology. Measurement results yield a saturated output power of 18.2 dBm with a peak PAE of 15.3% under static (continuous-wave) operation, and high-speed OOK modulation (upto 1Gbps and beyond) is demonstrated with high average efficiency.

A 60 GHz same-channel full-duplex CMOS transceiver and link based on reconfigurable polarization-based antenna cancellation

This paper describes a direct-conversion 45nm SOI CMOS 60 GHz transceiver for same-channel full duplex applications. A novel polarization-based wideband self-interference cancellation (SIC) technique in the antenna domain is described that can be reconfigured from the IC. In order to achieve the high levels of required SIC, a second RF cancellation path from the transmitter output to the LNA output with >30 dB gain control and >360° phase control is also integrated. The TX and RX share the same LO to reduce the impact of phase noise on SIC. Antenna and RF cancellation together enable >70 dB of total self-interference suppression even in the presence of nearby reflectors. In conjuction with digital SIC impemented in MATLAB, a same-channel full-duplex link is demonstrated over 0.7 m. To the best of our knowledge, this work demonstrates the first fully-integrated full-duplex transceiver front-end and mm-wave link. While not our focus, the transceiver also achieves state-of-the-art saturated output power of +15 dBm, peak TX efficiency of 15.3% and RX NF of 4 dB.