Kung-Hong Lee

New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications

A novel EEPROM memory cell with new program and erase operations fabricated by standard CMOS logic process is presented. The cell which consists of two N-Type MOSFET transistors in series is programmed by select gate controlled channel hot hole and erased by channel hot electron injection along with more than 10/sup 5/ cycles of endurance and 1000 hours of data retention at 150/spl deg/C. Without an additional P-well or N-well serving as the coupling gate, the area of a bit can be as small as 8F/sup 2/, the smallest area reported for single-poly EEPROM cells.

High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications

A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal–oxide–semiconductor (CMOS) logic process is presented. The cell which consists of two metal–oxide–semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 105 cycles, and 1000 h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.

Self-convergent scheme for logic-process-based multilevel/analog memory

A multilevel/analog electrically erasable programmable read only memory cell fabricated by standard CMOS logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE subcircuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.

Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory

A novel multilevel/analog electrically erasable programmable read only memory (EEPROM) cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme is proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE sub-circuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.

Embedded ultra high density flash memory cell and corresponding array architecture

A novel flash memory cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process and its corresponding array architecture is presented. The cell which consists of two metal-oxide-semiconductor field effect transistors (MOSFET) in series is programmed by channel current induced drain avalanche hot hole and erased by channel hot electron injection. With novel operation principles and array architecture, a feature-sized n-MOSFET per non-volatile memory bit is successfully demonstrated and the CMOS-process-based flash cell size can be as small as multi-gated flash memory. The smallest bit area of a CMOS-process-based flash memory cell with good programming and erasing characteristics along with endurance up to 105 cycles, 10 years excellent read disturbance and data retention characteristics of data retention at 150°C is proposed. With its small cell size and full compatibility with standard CMOS logic process, the novel flash memory cell can be easily adapted in highly integrated very large scale integration (VLSI) systems.