Kunihiko Gotoh

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

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A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power

Technology

A 10 b 125 MS/s pipelined ADC uses a new front-end circuit and consumes 40 mW from a 1.8 V supply. The ADC is implemented in a 0.18 /spl mu/m CMOS process and has an active area of 1.1/spl times/0.6 mm/sup 2/. Measured INL (integral nonlinearity) and DNL (differential nonlinearity) are within /spl plusmn/0.7 LSB, and /spl plusmn/0.5 LSB, respectively. Peak SNDR is 53.7 dB with a 2 MHz input.

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

An I/O transceiver for scalable multiprocessor systems with 1.25 Gb/s parallel bandwidth and 7.7 ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and inter-wiring skew across 20 m cable connections. Phase-interpolator-based clock recovery integrates multiple I/O links that can tolerate slight differences in frequencies between incoming and internal reference clocks. A differential partial-response detection (DPRD) receiver ensures low latency equalization for skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate up to 6.4 ns inter-wiring skew for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer, basic control, which maximizes data rate and minimizes power consumption without external manual adjustment, adapting from onboard PCB traces to 20 m twisted-pair cables.

A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 /spl mu/m CMOS

This paper describes a low-voltage design for a pipelined A/D converter that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output range of all MDACs by 50% compared with the ADCpsilas input. We designed a 10-b pipelined ADC with the proposed 2b-MDAC. The fabricated ADC using a 90-nm CMOS process is able to operate in 2.0-Vpp full-swing input at a 1.0-V supply in spite of it using conventional op-amps, and has SNDR/SFDR of 57.5 dB/69.0 dB at 30 MS/s with only 3.4 mW.

A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking

This paper describes a low-voltage design for a pipelined ADC that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output ranges of all MDACs by 50% compared to the ADCs input. We designed a 10-b pipelined ADC with the proposed front-end MDAC using a 90-nm CMOS process. The ADC achieved 2.0-Vpp rail-to-rail operation at only a 1-V supply and a 57.5-dB SNDR with only 3.4mW at 30MS/s despite using conventional folded-cascode op-amps.