Kunihiko Tsunedomi

A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature

A single-chip fail-safe microprocessor has been developed. It contains two processor cores and realizes self-checking feature by comparing the processing results of the two processor cores. In order to overcome redundant input disagreement problem, two mechanisms have been implemented. The one is input data exchange mechanism used with bus comparison feature. The other is memory data comparison and copy mechanism. With the memory data comparison mechanism, input data comparison overhead can be reduced, which is especially useful for short period control task with many input data. The microprocessor utilizes 0.18mum CMOS process and integrates 512KB RAM and 25M transistors random logic in a 14.75mm x 14.75mm die. With the developed microprocessor, the size of a fault-tolerant controller can be reduced, which makes it easy to embed fault-tolerant controllers into equipments controlled

High Performance and Cost-Effective Electronic Controller Architecture for Powertrain Systems

Electronic controllers for powertrain systems are required to meet the demands for increased system performance and functionality at reasonable cost. It is indispensable to examine the solutions from a range of view points synthetically for cost optimization. This paper describes a cost-effective hardware and software architecture of the electronic controllers for powertrain systems. A new method for noise reduction of a switching regulator, and a low standby current wakeup solution are also discussed as further functions needed for high performance powertrain systems.