Kenichi Kurosawa

Design and evaluation of the high performance multi-processor server

The paper discusses the architecture and performance of a prototype RISC multi-processor server designed for a business system like OLTP (online transaction processing). The combination of a low-latency cache-to-cache copy and an 8-way highly interleaved main memory realize high performance for the OLTP program. We analyzed the activity of the multi-processor system when executing the OLTP program by using the trace-driven simulator including kernel execution. The main findings are that: cache misses due to task migration and ping-ponging of kernel shared data occupy a larger part of the total misses, especially in a large cache capacity because of intensive I/O activities; and the low-latency cache-to-cache copy is very effective because 50-60% of the data read accesses are supplied by the cache-to-cache copy in a large cache capacity.<<ETX>>

High performance integrated Prolog processor IPP

To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed. A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an IPP architecture is presented. Based on the Prolog instruction set, which is an extension of Warrens, the Prolog compiler introduces new functions such as indexing by the optimal argument and global register assignment across determinate built-in predicates. The performance of the IPP for the append program is 1 million logical inferences per second, which is the highest possible for a sequential processor. In the 8-queen program a considerable speed-up is obtained by the new functions.

Cost-Effective and Fault Tolerant Vehicle Control Architecture for X-by-Wire Systems (Part 2: Implementation Design)

X-by-Wire systems are expected to enhance vehicle driving performance and safety. This paper describes an electronic platform architecture for X-by-Wire systems that satisfies both cost-effectiveness and dependability. In the first part of this paper (Part 1), we have proposed a new electronic architecture based on a concept of autonomous decentralized systems. In the latter part (Part 2), the proposed architecture implementation to the actual vehicle control systems will be discussed. We clarify that, due to system level redundancy the proposed architecture provides, vehicle control systems can basically consist of low cost fail-silent nodes. Furthermore, for cost optimization, considering a tradeoff between hardware cost and fault detection coverage, we design a suitable hardware architecture for each node according to node function.

Incremental update method for resource-constrained in-vehicle ECUs

An increase in the amount of program code used in the firmware of electronic control units (ECUs) in vehicles has led to an increase in updates after sales to resolve bugs in the program code. In this situation, automakers are beginning to introduce over-the-air firmware update technology currently used in the mobile phone industry. We developed an incremental update method based on BSDiff and demonstrated its application to resource-constrained microcontrollers in ECUs. We implemented the method using a Renesas RH850/F1L simulator and evaluated the memory usage and compression ratio. We demonstrated that the proposed method is applicable to in-vehicle ECUs.

Performance evaluation of Integrated Prolog Processor IPP

The IPP was developed to realize high-speed execution of Prolog and procedural languages on the same computer with less overhead. Previously developed optimization techniques such as clause indexing by optimal argument and global register assignment across determinate built-in predicates were intended to utilize mode information. The main extensions are as follows: to select as the optimal argument the variable that exists in a type checking predicate and to eliminate type checking from a clause code if such a predicate exists; and to detect unification failure as early as possible, and to resolve register conflicts by changing execution order in each unification that may fail and the remaining unification plus goal generation. The performance of the IPP for the append, quick sort, and eight-queen programs was found to be 1.1, 0.49, and 1.1 MLIPS, respectively.<<ETX>>