Kuniyoshi Yoshikawa

Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.

Degradation mechanism of flash EEPROM programming after program/erase cycles

The mechanism of degradation of flash EEPROM cell characteristics caused by program operation with the channel hot electron injection after program/erase (P/E) cycles are investigated. To clarify the relation between the degradation and oxide damage such as interface-states and oxide charges, the charge-pumping (CP) technique, transconductance (G/sub m/) measurements and cell endurance measurements are performed. In the degradation, a reduction of electron injection into the floating gate and a reduction of the G/sub m/ should be considered separately. The reduction of electron injection into the floating gate is found to be caused mainly by the interface-states located in the drain overlap region, not by charges trapped in the oxide. These interface-states are created during the initial step of program operation. On the contrary, a reduction of G/sub m/ is caused mainly by interface-states located around the drain edge. These are created during the final step of program operation.<<ETX>>

Process and device technologies for 16 Mbit EPROMs with large-tilt-angle implanted p-pocket cell

A reliable high-performance process and device technologies for the fabrication of a 0.6 mu m 16 Mbit CMOS EPROM have been developed. A novel cell structure called a LAP cell is proposed, which yields stable high performance in the 0.6 mu m regime. The important processes and device technologies are a large-tilt-angle implanted p-pocket (LAP) cell structure with 0.6 mu m gate length, a self-aligned source (SAS) technology, a poly-Si plugged-contact technology for CMOS devices via a novel multistep poly-Si deposition method, and a 0.8 mu m poly-Si shield isolation structure for high voltage circuits. It is noted that these technologies together with advanced lithography techniques will be sufficient for the manufacture of future 64 Mbit EPROMs and beyond.<<ETX>>

ONO inter-poly dielectric scaling for nonvolatile memory applications

The ONO (oxide/nitride/oxide) inter-poly dielectric thickness scaling effect on electric-field-leakage-current characteristics and charge retention characteristics in nonvolatile memories are investigated. Surface top-oxide thickness strongly affects the charge leakage and retention characteristics. Thicker than 3 nm top oxide can block hole injunction from the anode. Thick top oxide can reduce leakage current in both high and low electric field regions. Moreover, it can improve charge retention characteristics in nonvolatile memory cells. Therefore, a certain amount of top oxide is required to preserve good charge retention characteristics. SiN thickness scaling leads to an improvement in charge retention characteristics. Bottom oxide has an important role in suppressing electron leakage in a low electric field region. A degraded quality thin bottom oxide leads to charge retention capability degradation. Therefore, bottom-oxide quality and thickness control is an important subject for ONO thickness scaling. >

Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design

This paper, for the first time, describes the analytical expressions which explicitly relate single-cell characteristics to Flash array behaviour including statistical consideration. Since the bitline leakage current caused by over-erased cells and/or broad threshold voltage (Vt) distribution generates read/verify circuitry malfunctions and a degraded programming due to voltage drop, and charge-pump circuitry failure, this leakage are extensively analyzed to find the optimum operation biases, array Vt design, their allowed variations and bitline segmentation in the scaled multilevel cell generation.

Polyoxide thinning limitation and superior ONO interpoly dielectric for nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate. >

A reliable profiled lightly doped drain (PLD) cell for high-density submicrometer EPROM's and flash EEPROM's

A cell with a profiled lightly doped drain (PLD) structure is proposed for realizing high-density nonvolatile memories in the submicrometer range. The PLD cell has a surface n/sup -/ layer with a diffusion self-aligned (DSA) boron layer, in addition to a deep phosphorus n/sup -/ layer. This structure enhances hot-electron generation during write and significantly reduces it during read. The cell exhibits improved data retention as a result of reduced band-to-band tunneling leakage current. The optimized PLD cell combines improved soft-write immunity with high read current, and low gate-induced breakdown leakage with high-speed writing. Simulation results and measurements on a fabricated test structure confirm these characteristics. >

Lucky-hole injection induced by band-to-band tunneling leakage in stacked gate transistors

The band-to-band tunneling leakage characteristics of thin oxide MOSFETs are investigated by utilizing stacked-gate structure FETs. The behavior of threshold voltage variations under drain stress with open-circuit source is analyzed in detail. A simple lucky hole injection model is proposed to explain the behavior. Program-disturb phenomena in EPROM cells were well described by the model. The depletion layer along the channel formed by the applied drain voltage gives energy to cold holes created by band-to-band tunneling. Such lucky holes are injected easily and reach the gate electrode.<<ETX>>

Novel process and device technologies for submicron 4Mb CMOS EPROMs

High performance and reliable submicron EPROM technologies to realize 4Mb density and fast operation speed have been developed. The main key process technologies are (a) thin reliable inter-poly dielectrics, (b) SAC (Self Aligned Contact) using RTA (Rapid Thermal Annealing), and (c) low resistance polycide gate. The device uses 0.8µm N-well CMOS technology. Masked MLDD(Moderately Lightly Doped Drain) NMOS transistors are used in peripheral circuits. Submicron EPROM cell offers sufficiently fast write speed and soft-write endurance.

Bottom-oxide scaling for thin nitride/oxide interpoly dielectric in stacked-gate nonvolatile memory cells

The authors present results concerning the nitride-oxide (NO) interpoly dielectric in nonvolatile memories. Optimized NO films with a thick top oxide and a thin nitride structure offer sufficient charge retention capability in the 12-nm effective oxide thickness region. However, this structure shows an anomalous threshold voltage increase due to the back tunneling of electrons from the NO film to a floating gate. Such electrons can be injected into the NO film during programming and baking. The magnitude of this voltage depends on the NO film structure and the electric field during the program and bake procedure. Therefore, these phenomena must be taken into consideration in designing the cell structure and its operating conditions. The results obtained are also useful when considering ONO (oxide-nitride-oxide) scaling in the thin bottom-oxide region for nonvolatile memory applications. >