Yoichi Ohshima

Degradation mechanism of flash EEPROM programming after program/erase cycles

The mechanism of degradation of flash EEPROM cell characteristics caused by program operation with the channel hot electron injection after program/erase (P/E) cycles are investigated. To clarify the relation between the degradation and oxide damage such as interface-states and oxide charges, the charge-pumping (CP) technique, transconductance (G/sub m/) measurements and cell endurance measurements are performed. In the degradation, a reduction of electron injection into the floating gate and a reduction of the G/sub m/ should be considered separately. The reduction of electron injection into the floating gate is found to be caused mainly by the interface-states located in the drain overlap region, not by charges trapped in the oxide. These interface-states are created during the initial step of program operation. On the contrary, a reduction of G/sub m/ is caused mainly by interface-states located around the drain edge. These are created during the final step of program operation.<<ETX>>

Process and device technologies for 16 Mbit EPROMs with large-tilt-angle implanted p-pocket cell

A reliable high-performance process and device technologies for the fabrication of a 0.6 mu m 16 Mbit CMOS EPROM have been developed. A novel cell structure called a LAP cell is proposed, which yields stable high performance in the 0.6 mu m regime. The important processes and device technologies are a large-tilt-angle implanted p-pocket (LAP) cell structure with 0.6 mu m gate length, a self-aligned source (SAS) technology, a poly-Si plugged-contact technology for CMOS devices via a novel multistep poly-Si deposition method, and a 0.8 mu m poly-Si shield isolation structure for high voltage circuits. It is noted that these technologies together with advanced lithography techniques will be sufficient for the manufacture of future 64 Mbit EPROMs and beyond.<<ETX>>

ONO inter-poly dielectric scaling for nonvolatile memory applications

The ONO (oxide/nitride/oxide) inter-poly dielectric thickness scaling effect on electric-field-leakage-current characteristics and charge retention characteristics in nonvolatile memories are investigated. Surface top-oxide thickness strongly affects the charge leakage and retention characteristics. Thicker than 3 nm top oxide can block hole injunction from the anode. Thick top oxide can reduce leakage current in both high and low electric field regions. Moreover, it can improve charge retention characteristics in nonvolatile memory cells. Therefore, a certain amount of top oxide is required to preserve good charge retention characteristics. SiN thickness scaling leads to an improvement in charge retention characteristics. Bottom oxide has an important role in suppressing electron leakage in a low electric field region. A degraded quality thin bottom oxide leads to charge retention capability degradation. Therefore, bottom-oxide quality and thickness control is an important subject for ONO thickness scaling. >

A reliable profiled lightly doped drain (PLD) cell for high-density submicrometer EPROM's and flash EEPROM's

A cell with a profiled lightly doped drain (PLD) structure is proposed for realizing high-density nonvolatile memories in the submicrometer range. The PLD cell has a surface n/sup -/ layer with a diffusion self-aligned (DSA) boron layer, in addition to a deep phosphorus n/sup -/ layer. This structure enhances hot-electron generation during write and significantly reduces it during read. The cell exhibits improved data retention as a result of reduced band-to-band tunneling leakage current. The optimized PLD cell combines improved soft-write immunity with high read current, and low gate-induced breakdown leakage with high-speed writing. Simulation results and measurements on a fabricated test structure confirm these characteristics. >

Lucky-hole injection induced by band-to-band tunneling leakage in stacked gate transistors

The band-to-band tunneling leakage characteristics of thin oxide MOSFETs are investigated by utilizing stacked-gate structure FETs. The behavior of threshold voltage variations under drain stress with open-circuit source is analyzed in detail. A simple lucky hole injection model is proposed to explain the behavior. Program-disturb phenomena in EPROM cells were well described by the model. The depletion layer along the channel formed by the applied drain voltage gives energy to cold holes created by band-to-band tunneling. Such lucky holes are injected easily and reach the gate electrode.<<ETX>>

Flip chip underfill reliability of CSP during IR reflow soldering

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

Bottom-oxide scaling for thin nitride/oxide interpoly dielectric in stacked-gate nonvolatile memory cells

The authors present results concerning the nitride-oxide (NO) interpoly dielectric in nonvolatile memories. Optimized NO films with a thick top oxide and a thin nitride structure offer sufficient charge retention capability in the 12-nm effective oxide thickness region. However, this structure shows an anomalous threshold voltage increase due to the back tunneling of electrons from the NO film to a floating gate. Such electrons can be injected into the NO film during programming and baking. The magnitude of this voltage depends on the NO film structure and the electric field during the program and bake procedure. Therefore, these phenomena must be taken into consideration in designing the cell structure and its operating conditions. The results obtained are also useful when considering ONO (oxide-nitride-oxide) scaling in the thin bottom-oxide region for nonvolatile memory applications. >

0.6 mu m EPROM cell design based on a new scaling scenario

A novel scaling guideline is proposed for further scaling of EPROM (electrically programmable ROM) cells. Lateral and vertical scaling factors are independently introduced to clarify the scaling effects on cell reliabilities and performances. Based on the proposed scaling scenario, device dimensions and operation voltage designs for 16-Mb EPROM cells are given. 0.6- mu m EPROM cells have been fabricated and the validity of the guideline has been experimentally confirmed.<<ETX>>

A 3.3 V operation nonvolatile memory cell technology

The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<<ETX>>

Threshold voltage instability and charge retention in nonvolatile memory cell with nitride/oxide double-layered inter-poly dielectric

The authors present novel results concerning thin NO (nitride/oxide) double-layered interpoly dielectric in nonvolatile memories. Optimized NO films with thick top-oxide and thin nitride structure offer sufficient charge retention capability in the 10 nm effective oxide thickness region. However, this structure shows an anomalous threshold voltage increase due to the back tunneling of electrons which can be injected into the NO film during programming and baking. The magnitude of this voltage depends on the NO film structure and the electric field during the program or bake procedure. Therefore, these phenomena must be taken into consideration in designing the cell structure and its operating conditions. The results obtained are also effective in considering ONO (oxide/nitride/oxide) scaling in the thin bottom-oxide region.<<ETX>>