Kazuhito Narita

ONO inter-poly dielectric scaling for nonvolatile memory applications

The ONO (oxide/nitride/oxide) inter-poly dielectric thickness scaling effect on electric-field-leakage-current characteristics and charge retention characteristics in nonvolatile memories are investigated. Surface top-oxide thickness strongly affects the charge leakage and retention characteristics. Thicker than 3 nm top oxide can block hole injunction from the anode. Thick top oxide can reduce leakage current in both high and low electric field regions. Moreover, it can improve charge retention characteristics in nonvolatile memory cells. Therefore, a certain amount of top oxide is required to preserve good charge retention characteristics. SiN thickness scaling leads to an improvement in charge retention characteristics. Bottom oxide has an important role in suppressing electron leakage in a low electric field region. A degraded quality thin bottom oxide leads to charge retention capability degradation. Therefore, bottom-oxide quality and thickness control is an important subject for ONO thickness scaling. >

A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl mu/m/sup 2/ has been obtained for the 0.25 um design rule. To minimize the cell size, a floating gate is isolated with a shallow trench isolation (STI) and a slit formation by a novel SiN spacer process, which has made it possible to realize a 0.55 /spl mu/m-pitch isolation at a 0.25 /spl mu/m design rule. Another structural feature integral to the cell and its small size is the borderless bit-line and source-line contacts which are self-aligned with the select-gate. The proposed NAND cell with the gate length of 0.2 /spl mu/m and the isolation space of 0.25 /spl mu/m shows a normal operation as a transistor without any punch-through. Therefore, this 5F/sup 2/ NAND STI cell technology is essential to realize a low cost flash memories of 256 Mbit and 1 Gbit for mass-storage applications.

A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories

This paper describes a self-aligned Shallow Trench Isolation (STI) process integration to realize a low cost and high reliability 1 Gbit NAND flash memory. Peripheral low voltage CMOS transistors, high voltage transistors and small 5F/sup 2/ memory cells can be fabricated at the same time by using the self-aligned STI process. The advantages are as follows. (1) The number of process steps is reduced to 60% in comparison with a conventional process. (2) a high reliability of the gate oxide is realized even for high voltage transistors because the gate electrode does not overlap the trench corner. (3) A tight distribution of the threshold voltages (2.0 V) in a 2 Mbit memory cell array is achieved due to a good uniformity of the channel width in the self-aligned STI cells. Therefore this process integration combines a low cost with a high reliability for a manufacturable 1 Gbit flash memory.

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.

A 16 ns 1 Mb CMOS EPROM

A 64 K*16-b CMOS EPROM which achieves 16-ns access time using differential sensing with a constant-bias circuit is described. A compact test sense amplifier circuit in parallel with the main sense amplifier guarantees sufficient threshold voltage shift for the programmed cell for high-speed sensing. Complementary data are programmed into the pair of FAMOS transistors, which form one memory cell. The device is fabricated with double-layer-metal, 0.8- mu m n-well CMOS technology.<<ETX>>

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design

In a VLSI memory, noise generated by its own operation is a serious problem. The noise disturbs data sensing, especially in EPROMs which have a single-ended sensing scheme. To develop high-density and high-speed EPROMs, it is necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed. High-noise-immunity circuit techniques for stable data sensing and high-speed access time are proposed. These are divided bit-line layout, reference line with dummy bit lines, and a chip-enable transition detector. Using these circuit techniques and 0.8- mu m n-well CMOS technology, a 512 K*8-b CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm*15.30 mm, and it is assembled in a 600-mil cerdip package. >

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs. >

A 3.3 V operation nonvolatile memory cell technology

The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<<ETX>>

A new MOSFETs degradation induced by gate current in off-state condition

A PMOSFET degradation phenomenon induced by gate current in the off-state condition was studied experimentally for single-drain and lightly-doped-drain (LDD) structures. It is found that scaling down the gate length causes the gate bias condition where the fastest degradation is observed to shift from a condition of maximum gate current to one of zero gate voltage. This indicates a new constraint for scaling PMOSFETs. The hot-electron induced punchthrough (HEIP) effect has been considered one of the serious constraints for utilizing the single-drain structure, as well as for high-voltage applications. Effective channel length can be reduced significantly by HEIP effects in the on-state condition, but once the off-state drain leakage current increases, the off-state stress becomes more severe than the on-state HEIP effect

Process technologies for a 16 ns high speed 1 Mb CMOS EPROM

An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability. Process and device parameters are summarized. An 0.8-&mu;m N-well CMOS, 1 poly Si+1 MoSi polycide double metal technology is used. To fabricate 5-V and 12.5-V high-voltage NMOS and PMOS transistors simultaneously, masked lightly-doped-drain structures are used