Kunpei Yamada

New fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

As electronic parts increase its performance and miniaturize in its size, package substrates are demanded to be thinner and higher in density. But higher density substrates using insulating films give higher warpage values when they are very thin, due to its low modulus. Packages with glass-cloth prepreg as its outer-layer have lower warpage, but making a 40 μm pitch package with them are difficult because it cannot adapt to the semi-additive method. Conventional insulating films can be applied to the semi-additive method; however, a process of roughing the surface of the insulating films by chemicals is required, causing the limitation of material of insulating films. Therefore, we developed a new technology of semi-additive primer (SAPP) with glass-cloth prepregs which allows higher density and lower warpage for substrates. Under 30 μm pitch wiring of SAPP applied substrates were easier compared to conventional substrates made from the insulating film semi-additive method. Also, the roughening process (Ra=0.50–0.60 μm) of conventional insulating films to achieve adhesion strength with plated copper makes high density wiring difficult. But the new SAPP system has a surface roughness of Ra <0.25 μm with high adhesive strength which allows easy high density wiring. It has been made clear that by providing a new adhesive-agent layer, peel strength equivalent to that of the roughened insulating film (0.7 kN/m or more) can be obtained with sufficient reliability. The thinner package boards consisting of our new low-CTE and high modulus insulation prepreg E-700G(R) and SAPP have lower warpage than that of build-up structure and coreless structure using conventional insulating films. The package substrates made of SAPP with E-700G(R) core show low coefficient of thermal expansion (9–10 ppm/°C) and high modulus of tensile elasticity (32 GPa), with 20 μm pitch wiring possible.

Cavity down AlN PGA with inter-polyimide wiring

A low-thermal-resistance, high-speed pin-grid-array (PGA) package is discussed. To obtain low thermal resistance, a silicon chip was soldered onto a metallized aluminum nitride ceramic substrate that directly contacts an air-cooled fin (a cavity-down structure). Low propagation delay was realized by placing signal lines between low-dielectric-constant polyimide layers that were coated on the substrate. The thermal resistance from the silicon chip to the air environment was 2.7 degrees C/W with a 20-mm-high fin when the air velocity was 2 m/s. The self-inductance of the longest signal line was 20 nH, and the capacitance between the longest signal lines was 1.7 pF. The helium leakage level was about 10/sup -9/ atm-cm/sup 3//s even after 24 cycles in a thermal cycle test from -55 degrees C to 150 degrees C.<<ETX>>

Low thermal resistance AlN PGA with low inductance of power lines

A low-thermal-resistance and high-speed pin-grid-array (PGA) package with low-inductance power lines was proposed, and its feasibility was confirmed. To obtain low-inductance power lines, the wiring system in the package kept power-line layers and signal-line layers separate. Low inductance of power lines was realized by using conductive layers with a large area in an aluminium nitride (AlN) substrate and arranging the power pins just under the silicon chips. A high signal-propagation speed was realized by sandwiching radial signal lines between low-dielectric-constant polyimide layers. To obtain low thermal resistance, a silicon chip was soldered onto the metallized AlN ceramic substrate. High thermal conductivity of AlN ceramics and the arrangement of pins on the AlN substrate surface opposite the side of the silicon chip resulted in low thermal resistance of the package. The package on the printed wiring board had a thermal resistance of 3.0 degrees C/W at an air velocity of 1 m/s using a 14-mm-high aluminium cooling heat sink. The self-inductance of the power lines was 1.4 nH in the package substrate without pins and bonding wires.<<ETX>>