Kuo Hsing Kao

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kanes direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.

Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-onsource-only tunnel field-effect transistor simulations.

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors

We develop a model for the tunnel field-effect transistor (TFET) based on the Wentzel-Kramer-Brillouin approximation which improves over existing semi-classical models employing generation rates. We hereby introduce the concept of a characteristic tunneling length in direct semiconductors. Based on the model, we show that a limited density of states results in an optimal doping concentration as well as an optimal material’s band gap to obtain the highest TFET on-current at a given supply voltage. The observed optimal-doping trend is confirmed by 2-dimensional quantum-mechanical simulations for silicon and germanium.

Reliability Mechanisms of LTPS-TFT With

In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the gate dielectric is observed for the PBS and PBTI of the LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the LTPS-TFT.

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Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k · p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Γ and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-hole-like valence band is strongly coupling to the conduction band at the Γ point even in the presence of strain based on the 30-band k · p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-t...

Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

Tensile strained Ge tunnel field-effect transistors: k-p material modeling and numerical device simulation

For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (~ 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. ~ 67mV/dec) and excellent on-off ratio (>106) for both n and p channel devices. Threshold voltage (VTH) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.

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The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher on-state tunneling current than the transistor with a gate on the channel only. In the presence of a counterdoped pocket in the source region underneath the gate electrode, the vertical tunneling component dominates over the unwanted lateral tunneling component, and the performance variability is reduced compared to its no-pocket configuration. The optimal pocket thickness, which is a tradeoff between realistic gate work function and the desired SS, is dependent on the bandgap, electron or hole effective mass, permittivity, and tunneling orientation of semiconductor materials, as analyzed in detail in this paper. A numerical procedure is provided to determine the optimal pocket thickness for arbitrary semiconductor materials.

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In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of devices performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.