Kurt Taylor

Stress modeling of Cu/low-k BEoL - application to stress migration

Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using Finite Element Analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD (inter-layer dielectric) properties, ILD stack and metal line width. The concept of a SM Risk Index is proposed to assess BEoL stress migration reliability from the stress perspective. Comparison of the SM Risk Index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

New findings of NBTI in partially depleted SOI transistors with ultra-thin gate dielectrics

This work presents, for the first time, a comprehensive study of NBTI in partially depleted (PD) SOI PMOSFETs with gate dielectric thickness as small as /spl sim/11/spl Aring/ for understanding of both general and SOI-specific NBTI mechanisms. Body tied (BT) transistors will be studied intensively to interpret their worse NBTI degradation than floating body (FB). NBTI self-healing will be also investigated.

Bias and temperature dependent hot-carrier characteristics of sub-100 nm partially depleted SOI MOSFETs

In this paper, we report hot-carrier behavior of sub-100 nm partially depleted SOI MOSFETs at room (25C) and high temperature (100C) under various stress conditions. It was observed that V/sub G/=V/sub D/ was the worst case and more sensitive to temperature variation. SOI is more sensitive to operation temperature than bulk transistors. Hot carrier activation energy has also been extracted in the experiments.

Polarity dependent reliability of advanced MOSFET using MOCVD nitrided Hf-silicate high-k gate dielectric

We report reliability of MOSFETs with MOCVD nitrided Hf-silicate (HfSiON) high-k gate dielectric. HfSiON has shown superior electrical characteristics, such as low leakage relative to SiO/sub 2/ and high mobility compared to other high-k gate dielectrics. SILC is found to be comparable to SiO/sub 2/ and better than Hf-silicate without nitridation. TDDB and BTI reveal significant difference between inversion and accumulation mode. Polarity-dependent charge trapping and defect generation are observed and attributed to asymmetric band diagram as well as dissimilar charging processes in two stress modes. Trap-assisted tunneling is evidenced by its strong temperature dependence. Charge pumping tests indicate higher interface density compared to SiO/sub 2//Si. The Weibull slope is determined to be about 3, showing robust wear-out quality of the high-k dielectric.

DC and AC hot-carrier characteristics of partially depleted SOI MOSFETS with ultra-thin gate dielectrics

With the introduction of ultra-thin (<15/spl Aring/) gate dielectrics especially DPN (decoupled plasma nitridation), which has a significantly higher nitrogen concentration, and thus a higher dielectric constant, various transistor reliability issues such as DC and AC HCI (hot carrier injection) characteristics need to be revisited and compared with that of previous generation technologies, such as furnace-NO (F-NO). In this paper, the following HCI characteristics will be carefully investigated and compared: furnace-NO versus DPN; NFET versus PFET: bulk versus SOI; polythickness effect; HCI temperature and thickness dependence in DPN.