Richard C. Blish

Temperature cycling and thermal shock failure rate modeling

Combining the Coffin-Manson formula with a lognormal distribution continues to be an effective method to model the effects of thermal stressing upon VLSI IC package reliability. This approach is applied to Thin Film Cracking (TFC) and several other failure mechanisms relevant to IC packages. The Coffin-Manson exponent, m, is found to lie in one of three relatively narrow ranges: m for ductile metal fatigue is /spl sim/1-3 m for commonly used IC metal alloys and intermetallics is /spl sim/3-5, while m for brittle fracture is /spl sim/6-8.

Board level solder reliability versus ramp rate and dwell time during temperature cycling

Effects of ramp rate and dwell time are studied through laboratory results and a nts (DOE) using finite element analysis (FEA) incorporating stress/strain and plastic work history. Results demonstrate that solder joint fatigue life is more sensitive to dwell time than ramp rate during thermal cycling. A nonlinear relationship exists between solder fatigue life (mean time to failure, MTTF) and dwell time. Increasing dwell time past 20 min has a minimal effect on the acceleration factor or lifetime. Modeling shows that the acceleration factor increases by a factor of 1.23 for a specific ball grid array (BGA) assembly when the test condition changes from a slow ramp/long dwell (single chamber) to a fast ramp/short dwell (dual chamber). Experiments were performed to validate the FEA modeling. Different ramp time/dwell times were achieved by modulating the temperature profile in a single chamber oven. If dwell time changes from 5 to 10 min with an invariant ramp time of 5 min, apparent MTTF decreases by 55%. However, if the invariant dwell time is 10 min, MTTF remains practically the same as the ramp time increases from 5 to 10 min. These test results are consistent with modeling predictions. The focus of temperature cycling tests should not be on number of chambers, nor upon ramp rate, but upon dwell time. We recommend 8 to 10 min dwell at a high temperature of 125/spl deg/C.

Investigation of Cu/low-k film delamination in flip chip packages

Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL technology. To study the dependence of Cu/low-k delamination on package underfill material properties and BEoL stack up configuration, a multi-level finite element analysis modeling technique was developed to perform fracture mechanics analysis for a high performance organic flip chip package with Cu/low-k backend technology. Realistic patterned interconnect features were explicitly modeled at the BEoL level. Global analysis revealed the possibility of two failure modes: near-bump delamination and corner delamination. Modeling and experimental results demonstrated that the reduced elastic modulus of the inter-layer dielectric lead to greater probability of CPI-related delamination for both failure modes. Replacing oxide by low-k dielectric resulted in a 3times increase of energy release rate. Hybrid BEoL stack up can effectively reduce the energy release rate by approximately 40% vs. all low-k BEoL stack up. The impact of package underfill modulus on CPI-related reliability is two fold: while reducing underfill modulus helps to prevent corner delamination, it accelerates the near-bump delamination. Higher underfill CTE (coefficient of thermal expansion) increased the risk of Cu/low-k delamination. The modeling also indicated that die size is not the limiting factor for CPI reliability

Simulation and experiments of stress migration for Cu/low-k BEoL

Stress migration (SM) or stress-induced voiding experiments were conducted for two back-end-of-line (BEoL) technologies: Cu/FTEOS and Cu/low-k. Experiments have shown the mean time to failure (MTF) depends on inter-layer dielectric (ILD) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using finite element analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD properties, ILD stack and metal line width. The concept of an SM risk index is proposed to assess BEoL stress migration reliability from both stress and energy perspectives. Comparison of the SM risk index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress-induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

Stress modeling of Cu/low-k BEoL - application to stress migration

Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using Finite Element Analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD (inter-layer dielectric) properties, ILD stack and metal line width. The concept of a SM Risk Index is proposed to assess BEoL stress migration reliability from the stress perspective. Comparison of the SM Risk Index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

A physically based lifetime model for stress-induced voiding in interconnects

We use a simple closed-form lifetime model for stress-induced voiding (SIV) or stress migration for Al- or Cu-based interconnects. Stress-induced voiding is treated as a process of void nucleation/growth and stress relaxation through atomic diffusion driven by a stress gradient. We developed a physically based method of modeling atomic diffusion and void growth, which explicitly accounts for the dependence of void growth on several factors including stress, temperature, diffusivity, and effective modulus. Based on basic physics associated with void growth, we define zones as SIV plate, SIV long line, and SIV short line, respectively, i.e., the three sequential stages for the process of void growth, depending on a nondimensional time-dependent parameter ψ and the aspect ratio of the interconnect. Simple form solutions to the governing equations that describe void growth are then sought for each scenario separately. Time to failure (TTF) is calculated as a function of stressing temperature, mechanical stres...

Investigation and minimization of underfill delamination in flip chip packages

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (/spl psi/) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm//spl deg/C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm//spl deg/C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (/spl psi/), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.

Board level solder reliability vs. ramp rate & dwell time during temperature cycling

The effects of ramp rate and dwell time are studied through laboratory results and Design Of Experiments (DOE) using Finite Element Analysis (FEA) incorporating stress/strain and plastic work history. Results demonstrate that solder joint fatigue life is more sensitive to dwell time than ramp rate during thermal cycling. A non-linear relationship exists between solder fatigue life (Mean Time To Failure, MTTF) and dwell time. Increasing dwell time past 20 minutes has a minimal effect on the acceleration factor or lifetime. This study also reveals that a dual chamber test presents harsher stress conditions than a single chamber test (when comparing the same number of cycles/hour) for solder joints because of an associated longer dwell time (faster ramp rate has a lesser effect). Modeling shows that the acceleration factor increases by a factor of 1.23-fold for a specific BGA assembly when the test condition changes from single chamber to dual chamber. Experiments were performed to validate the FEA modeling. Different ramp time/dwell times were achieved by modulating the temperature profile in a single chamber oven. If dwell time changes from 5 minutes to 10 minutes with a ramp time of 5 minutes, apparent MTTF decreases by 55%. However, MTTF remains practically the same as the ramp time increases from 5 to 10 minutes, if dwell time is 10 minutes. These test results are consistent with modeling predictions. The focus of temperature cycling tests should NOT be on number of chambers, nor upon ramp rate, but upon dwell time. We recommend 8 minutes to 10 minutes dwell at a high temperature of 125/spl deg/C.

Flash memory under cosmic and alpha irradiation

Neutron and proton irradiation to simulate cosmic ray jeopardy were used to establish that NOR Flash memory (conventional floating polySi gate or ONO floating gate MirrorBit) soft error failure rate (cross section) is 3-5 orders of magnitude better than SRAM. Flash memory soft error rate for a given dose of alpha particle irradiation is much less than for the same dose from simulated cosmic rays.

Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages

Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element analysis (FEA) models were used to analyze the effect of underfill height and width on interfacial stresses in a typical organic flip chip package configuration. Peeling and shearing stresses were computed for a large combination of fillet heights and widths (15 times 16 = 240). Three locations of interest: die bottom corner/underfill, die edge/fillet top and fillet bottom/substrate, were studied. For each location, 3D surface plots were generated to depict the variation of shear/peel stress simultaneously with width and height. An analysis of variance (ANOVA) was conducted for the full factorial design of experiments (DOE) to quantify the effect of underfill fillet height and width on the numerically computed shear and peel stresses at each location. Interaction among these variables was permitted and studied, and was found to be significant in some cases. The dominant factor(s) governing interfacial stresses for each location was identified and optimum values recommended. Limited data, with corner fillet heights in the range ~2% to 70% of die thickness, suggested adequate reliability for most field applications. Additional data are required to further validate the results