Stephen G. Beebe

An automatic biasing scheme for tracing arbitrarily shaped I-V curves

A scheme for automated tracing of arbitrarily shaped I-V curves is presented. Tracing out the I-V curves for complicated device phenomena such as breakdown in bipolar transistors and latchup in CMOS structures using conventional device simulation techniques requires a priori knowledge of the shape of the I-V curve and thus is not suitable for exploring new device phenomena. This paper presents a dynamic load-line technique which adapts the boundary conditions as the trace progresses to ensure convergence. By monitoring the slope of the curve, an optimal boundary condition is determined for each point. The boundary condition consists of a voltage source and load resistance corresponding to a load line which is orthogonal to the differential resistance at each point. This orthogonality is defined in a coordinate system scaled by the DC resistance. Step size between points is also defined by this scaling and is varied according to a smoothness criterion. The algorithm guarantees fully automatic tracing of any I-V curve without prior knowledge of the curves characteristics. Its implementation is completely external to the device simulator, i.e., it simply sets up the boundary conditions to be used by the simulator. Curve tracing examples which validate the algorithm are discussed. >

ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit protection techniques such as the T-coil based ESD design are reviewed in detail. Package- and wafer-level charged device model (CDM) correlation issues are discussed. I/O, ESD devices, and metal interconnect effects are examined using very fast transmission line pulses (VF-TLP) and TLP.

ESD design challenges and strategies in deeply-scaled integrated circuits

Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer level CDM correlation issues are examined.

Next generation Stanford TCAD-PISCES 2ET and SUPREM 007

Different aspects of Process and Device Simulators developed at Stanford are demonstrated. For PISCES 2ET, a new transport model is benchmarked in comparison to other simplified formulations. Support utilities related to curve tracing are demonstrated. The modular integration of standard tools such SUPREM 4GS and SPEEDIE with a heterogeneous set of other simulators using an agent-based approach (007) is demonstrated.<<ETX>>

Virtual instruments for development of high performance circuit technologies

A set of virtual instruments based on computer-aided design tools for technology (TCAD) are described. These virtual instruments support the evaluation of new technologies for circuit applications, including both intrinsic and parasitic effects. Mixed-mode (circuit/device) simulation in both the frequency and time-domain is demonstrated including an example of a virtual network analyzer applied to evaluation of a GaAs FET. Virtual curve-tracing is demonstrated as a powerful means to obtain I-V curves and to zoom in on the regions of device characteristics where SPICE model parameters can effectively be extracted and parasitic effects such as failure mechanisms due to electrostatic discharge (ESD) can be analyzed. Finally large signal distortion behavior analyzed based on the device simulation using the harmonic balance (HB) method is demonstrated with application to extraction of intermodulation (IM) distortion in bipolar transistor circuits.

Investigation on the Behavior of Stacked Devices Within Output Drivers Under ESD Conditions

This work investigates the robustness of a stacked or cascoded driver under electrostatic discharge (ESD) events. Using output driver circuits in an actual I/O system with predrivers and rail-based power clamps, the impacts of all possible predriver connections and stacked-driver sizing are examined with the very fast transmission line pulse. It is verified that, when the input of the predriver connected to the top MOSFET is grounded, the failure current (IT2) is improved by ~ 110%, compared to the worst case where both predriver inputs are tied to VDD. Also, a simple trigger circuit which guarantees the electrical connection for better ESD immunity is proposed.

Field Effect Resistor, a single-device-at-pad solution for ESD protection in deeply scaled SOI technology

In this paper, the FER is shown to be a possible candidate for ESD protection in deeply scaled SOI technology. It2 of above 50 mA/µm and capacitance below 0.6 fF/µm are achieved. Despite the FERs higher resistivity than SOI diode, its major advantage is the dual-directional current shunting capability, such that ESD protection between I/O pads and power buses can be achieved with a single-device solution at the pad instead of several devices. Therefore, this device expands the conventional ESD design space for trading off parameters such as resistivity, Ileak and capacitance. Results from measurements and TCAD simulations further instantiate the advantages of the FERs in current and future SOI technologies. For future technologies such as ultra-thin-film SOI and FinFET, better gate controllability can be achieved to sustain the inversion regions. Thus, the well doping can be increased to lower the resistivity, making the FER more suitable for I/O protection.