Kwang-Il Oh

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.

A 500MHz DLL with second order duty cycle corrector for low jitter

A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13mum CMOS process achieves an output duty error below plusmn1.6% within plusmn25% external input duty error. It has a 29.2 ps peak-to-peak jitter and a 3.8 ps RMS jitter

A clock delayed sleep mode domino logic for wide dynamic OR gate

A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18? CMOS technology. In addition, the sleep mode entrance power is reduced to 10-5 of the HS-domino logic [3].

A high performance low power dynamic PLA with conditional evaluation scheme

This paper proposes a high performance and low power dynamic CMOS PLA that minimizes active power consumption. The proposed PLA uses a conditional evaluation scheme to reduce short circuit power consumption during the evaluation phase. The proposed PLA reduces delay by 13.8%, dynamic power by 46%, and total power delay product (PDP) by 53.4% compared to the conventional clock-delayed PLA in a 0.25 /spl mu/m CMOS process technology.

Cancelation of a crosstalk induced noise in a DDR memory interface

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.

Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232]

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.

A low power SoC bus with low-leakage and low-swing technique

A novel low power SoC bus with low-leakage and low swing technique is proposed. The repeater used in the bus lines effectively reduces leakage power through stacking effect, not losing its logic values even in sleep mode. The proposed SoC bus reduces not only the leakage power in the normal active/sleep mode but also both dynamic and leakage power in the low swing operation mode. The proposed scheme reduces the total power by 44.5% compared to the conventional SoC bus architecture