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Dive into the research topics where Kwang-Ok Jeong is active.

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Featured researches published by Kwang-Ok Jeong.


international symposium on low power electronics and design | 2003

An MTCMOS design methodology and its application to mobile computing

Hyo-sig Won; Kyosun Kim; Kwang-Ok Jeong; Ki-Tae Park; Kyu-Myung Choi; Jeong-Taek Kong

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsungs 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.


Archive | 2005

MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop

Hyo-sig Won; Kwang-Ok Jeong; Young-Hwan Kim; Bong-Hyun Lee


Archive | 2016

SEMICONDUCTOR DEVICE FOR TESTING LARGE NUMBER OF DEVICES AND COMPOSING METHOD AND TEST METHOD THEREOF

Hyo-sig Won; DaiJoon Hyun; Kwang-Ok Jeong


Archive | 2002

Clocked-scan flip-flop for multi-threshold voltage CMOS circuit

Kwang-Ok Jeong; Hyo-sig Won


Journal of Semiconductor Technology and Science | 2004

MTCMOS Post-Mask Performance Enhancement

Kyosun Kim; Hyo-sig Won; Kwang-Ok Jeong


Archive | 2014

DOUBLE PATTERNING LAYOUT DESIGN METHOD

Tae-Joong Song; Jae-Ho Park; Kwang-Ok Jeong


Archive | 2016

Method of designing layout of semiconductor device

Kwang-Ok Jeong


Archive | 2014

LAYOUT DESIGNING METHOD FOR DOUBLE PATTERNING

Tae-Joong Song; Jae-Ho Park; Kwang-Ok Jeong


Archive | 2014

Layoutentwurfsverfahren für Doppelstrukturierung Layout design method for double patterning

Tae-Joong Song; Jae-Ho Park; Kwang-Ok Jeong


ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications | 2004

Clock-free MTCMOS Flip-flops with High Speed and Low Power

Bong Hyun Lee; Young-Hwan Kim; Kwang-Ok Jeong

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Kyosun Kim

Incheon National University

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Bong Hyun Lee

Pohang University of Science and Technology

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