Hyo-sig Won

A 14 nm FinFET 128 Mb SRAM With V

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 VMIN with 200 mV improvement by NBL, and 0.47 VMIN for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved VMIN reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

_{\rm MIN}

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsungs 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

Enhancement Techniques for Low-Power Applications

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2-4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

An MTCMOS design methodology and its application to mobile computing

In this study, we implemented an auto-correction method for layout of 45 nm standard cells to get design-for-manufacturability (DFM) friendly design. The proposed method avoids lithography hotspot and particle defect, which are the source of systematic and random variation, by utilizing litho simulation and critical area analysis during optimization. In addition, to achieve maximum benefit of standard cell optimization, most of the recommended rules (RR) are applied to the standard cells. To assure the consistency of the optimization result, priority was given for each rule and the optimization is performed based on the priority. Using the proposed method, optimization time decreased tremendously compared to manual correction; therefore, the proposed layout optimization can handle thousands of standard cells with reasonable runtime. Verification results with manufacturing checking deck showed that DFM-friendly index improved by over 4.3% on optimized cells when compared to the original cells.

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

Thermal management, which dynamically throttles frequency and voltage, is de facto standard in high performance mobile SoC to sustain device surface temperature under specific level; and throttling must accompany with computation slowdown. To minimize performance loss, we present a new thermal management by using adaptive body bias which efficiently modulates speed and leakage current. The key problem is to optimize body voltage respect to performance as well as power in chip-to-chip process variation. We also propose a semicustom design flow with standard cells and commercial EDA tools for seamless adoption to commercial products. With the proposed method, we can reduce 12.3% of the quality loss caused by thermal management in a mobile SoC test vehicle. This is the first study and commercial use in thermal management at the best of our knowledge.

DFM optimization of standard cells considering random and systematic defect

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.

Thermal-aware body bias modulation for high performance mobile core

A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respectively, and the power consumption is reduced by 12% and 44%, respectively. Furthermore, the area of the SPSA is estimated to be 43% smaller than that of the ACSA. Although the SPSA has a 59% larger area than a dynamic pMOS sense amplifier, the area overhead can be mitigated by allocating a larger number of cells per bit-line (CpBL) because the performance of the SPSA is still better than that of the dynamic pMOS, even with a CpBL that is two times larger.

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

Since the manufacturing process has been scaled down under 65nm process, semiconductor industries have suffered from the yield loss although the total number of manufactured die has continuously increased. In order to overcome this ironic situation, industries have focused on the improvement of process technology, but reducing pattern size without a break makes this process improvement difficult. In this paper, we present the circuit techniques based on body and gate-length biasing to resolve this yield loss problem. Our application results show that up to 28% parametric yield can be improved by applying the proposed circuit techniques. In addition, the application of proposed methods does not need to have the specific platform since our methodology is quite easy to plug in general purpose application.

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85-5.88 times and 35%-70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.

Design techniques to Minimize the yield loss for general purpose ASIC/SOC Devices

From FinFET test vehicle data, outlier is discriminated based on Mahalanobis distance, large Silicon-to-SPICE gap (S2S gap) device is defined, and significant design attributes are analyzed as the root causes of them. In order to analyze this, attribute commonality is defined and calculated based on Monte-Carlo method to identify specific design attributes which are commonly and specifically observed in outlier and large S2S gap device. By narrowing down the design attributes by decision tree using the attribute commonality as decision criterion, the representative structure is identified. The methodology was applied to 14nm and 10nm FinFET with variety of actual layout structures used in product chip.