Kwang-Yell Seo

Growth of γ-Al2O3 thin films on silicon by low pressure metal-organic chemical vapour deposition

Abstract Metal-organic chemical vapour deposition of Al2O3 using aluminium isopropoxide (Al(OC3H7)3) and nitrous oxide (N2O) via thermal pyrolysis was investigated with the goal of producing high quality Al2O3p-Si(100) interfaces. From the X-ray diffraction analysis, the film was found to be a γ-Al2O3 heteroepitaxial film. The stoichiometry of the grown Al2O3 film was similar to that of sapphire observed from Auger electron spectroscopy. Room temperature capacitance-voltage measurements clearly reveal metal-insulator-semiconductor behaviour for samples with the Al2O3 insulator gate, and the interface state densities at the Al2O3p-Si heterointerface were approximately 1011 eV−1 cm−2, at levels centred in the silicon energy gap.

Structural properties of titanium dioxide films grown on p-Si by metal-organic chemical vapor deposition at low temperature

Abstract Metal-organic chemical vapor deposition of TiO 2 via pyrolysis using Ti (OC 3 H 7 ) 4 and N 2 O was investigated with the goal of producing TiO 2 epitaxial films on p-Si(100) substrates. X-ray diffraction analysis showed that the grown TiO 2 layer was a polycrystalline film. Auger depth profiles demonstrated that the TiO 2 /Si interface was relatively abrupt, and transmission electron microscopy verified the formation of an interfacial layer in the TiO 2 /Si interface and the formation of a polycrystalline TiO 2 thin film. These results indicate that the failure to form the TiO 2 epitaxial films originated from the formation of an interfacial amorphous layer at the initial growth stage.

Fabrication and characteristics of scaled SONOSFET nonvolatile memory devices for full-featured EEPROMs

Scaled SONOSFET nonvolatile memory devices were designed and fabricated using the n-well CMOS process technology with 1.5 /spl mu/m design rule in order to investigate the characteristics of scale-down devices. The ONO gate insulator of fabricated SONOSFETs were formed with a 18 /spl Aring/ tunneling oxide, 38 /spl Aring/ nitride and 37 /spl Aring/ blocking oxide. Memory window of 1.9 V was obtained with write pulse of +7 V, 2 sec and erase pulse of -7 V, 2 sec, and 1 V with /spl plusmn/7 V, 50 msec. Data retention after programming was achieved over 10 years.

Characterizations of MONOS structures with a superthin nitride film for the low voltage NVSM using TSC techniques

TSC (thermally stimulated current) technique has been applied to investigate the characteristics of MONOS (metal-oxide-nitride-oxide-semiconductor) structures with superthin nitride film of 46 /spl Aring/ thick for the low voltage NVSM. A new discharging model bans been developed and formulated for analysis of TSC curves due to memory traps such as the blocking oxide-nitride interface trap and the nitride bulk trap. By best fitting method, the blocking oxide-nitride interface traps are found to be energetically distributed in the range of 1.17/spl sim/1.18 eV below the top of the nitride conduction band with a density of N/sub ON/=2.3/spl times/10/sup 15/ cm/sup -2/ eV/sup -1/. The discharging mechanism can be explained that the holes trapped in the blocking oxide-nitride interface traps, distributed uniformly in energy, are first thermally excited into the nitride valence band, then drifted to the nitride-tunneling oxide interface, and finally tunneled into the Si valence band to contribute to TSC.

Fabrication and Device Performance of Tera Bit Level Nano-scaled SONOS Flash Memories

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of , 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.⡌ឫഀĀ᐀會Ā᐀㡆ﶖ⨀쁌ឫഀĀ᐀會Ā᐀遆ﶖ⨀郞ග瀀ꀏ會Āﶖ⨀〲岒Ā᐀會Ā᐀䁇ﶖ⨀젲岒Ā㰀會Ā㰀顇ﶖ⨀끩Ā㈀會Ā㈀ﶖ⨀䡪ഀĀ᐀會Ā᐀䡈ﶖ⨀Ā᐀會Ā᐀ꁈﶖ⨀硫ഀĀ저會Ā저ﶖ⨀샟ගĀ저會Ā저偉ﶖ⨀栰岒ഀĀ저會Ā저ꡉﶖ⨀1岒Ā저會Ā저Jﶖ⨀惝ග؀Ā؀會Ā؀塊ﶖ⨀ග䈀Ā切會Ā切끊ﶖ⨀⣟ගĀ搀會Ā搀ࡋﶖ⨀큭킢Ā저會Ā저恋ﶖ⨀桮킢Ā저會Ā저롋ﶖ⨀

An Investigation of Locally Trapped Charge Distribution using the Charge Pumping Method in the Two-bit SONOS Cell

The direct lateral profile and retention characteristics of locally trapped-charges in the nitride layer of the two-bit polysilicon-oxide-nitride-oxide-silicon (SONOS) memory are investigated by using the charge pumping method. After charges injection at the drain junction region, the lateral diffusion of trapped charges as a function of retention time is directly shown by the results of the local threshold voltage and the trapped-charges quantities.

Synaptic SONOS nonvolatile analog memories for artifical neural networks

In this paper, a new synapse cell with nonvolatile SONOS semiconductor memory device is proposed. The memory value, synaptic weights, can be changed incrementally. A novel SONOS synapse is used to read out the stored value. For the purpose of synapse implementation using SONOS NVSM, this work has investigated weight updating characteristics including multiplying characteristics. It is concluded that SONOS synapse cell has excellent characteristics for use as a synapse in artificial neural networks.