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Dive into the research topics where Sang-eun Lee is active.

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Featured researches published by Sang-eun Lee.


international reliability physics symposium | 2009

Post-cycling data retention failure in multilevel nor flash memory with nitrided tunnel-oxide

Wook Lee; Chang-Hyun Hur; Hyun-Min Lee; Hwanbae Yoo; Sang-eun Lee; B.H. Lee; Chan-Kwang Park; Ki-Joon Kim

Post-cycling data retention characteristics of a multilevel NOR flash memory with nitrided tunnel-oxide is presented. Results show that retention behavior is strongly related to the amount of interface trap generation rather than that of oxide trap, indicating detrapping from near interface trap is a major factor for threshold voltage shift. Process conditions including nitrogen concentration at the interface and subsequent annealing of nitrided tunnel-oxide by O2 are found to be related to the generation of interface trap and resultant postcycling retention.


Solid-state Electronics | 1997

Overcoming the fill factor limit of double sided buried contact silicon solar cells

Abasifreke Ebong; Sang-eun Lee

The double sided buried contact (DSBC) silicon solar cells have consistently demonstrated output parameters superior to those of its single sided counterparts. This is because the high surface recombination velocity of the single sided cells was reduced to minimum by the rear floating junction in conjunction with high quality silicon dioxide. However, the somewhat lower fill factor (FF) exhibited by single sided illumination of the structure can disappear if the bifacial testing equipment is used to properly characterize the cells. A 2D simulation has shown that a rear illumination of only 0.2 sun in conjunction with 1 sun front illumination, is quite adequate to bias the rear junction to a high voltage required to maintain good fill factor. This article discusses the fill factor of double sided buried contact silicon solar cells under single and double sided illumination.


symposium on vlsi technology | 2003

Highly manufacturable 90 nm NOR flash technology with 0.081 /spl mu/m/sup 2/ cell size

Y.J. Song; Sang-eun Lee; Tae-yong Kim; Jungin Han; Hungyu Lee; Sun-Young Kim; Junghwan Park; S.O. Park; Joonhuk Choi; Jaewoo Kim; Dae-Yup Lee; Myoung-kwan Cho; Kyu-Charn Park; Kinam Kim

A manufacturable 90 nm NOR Flash technology has been developed with extremely small cell size of 0.081/spl mu/m/sup 2/, which is the smallest cell size of NOR cell, for high density code storage memory featuring with low voltage operation. The small cell size of 0.081/spl mu/m/sup 2/ is successfully achieved with three key main technologies such as an advanced KrF lithography with off-axis illumination system, appropriate dielectric thin film and junction scaling and optimized oxidation encroachment of inter-poly oxide nitride oxide (ONO) and tunnel oxide.


ieee international conference on properties and applications of dielectric materials | 1997

Characterizations of MONOS structures with a superthin nitride film for the low voltage NVSM using TSC techniques

Sang-Bae Yi; Sam-Kyung Kuk; Sang-eun Lee; Byungcheul Kim; Kwang-Yell Seo

TSC (thermally stimulated current) technique has been applied to investigate the characteristics of MONOS (metal-oxide-nitride-oxide-semiconductor) structures with superthin nitride film of 46 /spl Aring/ thick for the low voltage NVSM. A new discharging model bans been developed and formulated for analysis of TSC curves due to memory traps such as the blocking oxide-nitride interface trap and the nitride bulk trap. By best fitting method, the blocking oxide-nitride interface traps are found to be energetically distributed in the range of 1.17/spl sim/1.18 eV below the top of the nitride conduction band with a density of N/sub ON/=2.3/spl times/10/sup 15/ cm/sup -2/ eV/sup -1/. The discharging mechanism can be explained that the holes trapped in the blocking oxide-nitride interface traps, distributed uniformly in energy, are first thermally excited into the nitride valence band, then drifted to the nitride-tunneling oxide interface, and finally tunneled into the Si valence band to contribute to TSC.


Archive | 2007

Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby

Sang-eun Lee; Y.J. Song


Archive | 2000

Method of forming contact structure in a semiconductor device

Soon-Moon Jung; Sun-cheol Hong; Sang-eun Lee


Archive | 2002

Apparatus for rotating a sample

Sang-eun Lee


Archive | 2002

Method of identifying and analyzing semiconductor chip defects

Sang-eun Lee; Jae-Sung Han


Archive | 2012

Case for a slate computer

Sang-eun Lee; Iksang Kim


Archive | 2012

Non-volatile memory systems

B.H. Lee; Jungin Han; Haebum Lee; Sang-eun Lee; Jung-Ro Ahn; Kyung-Jun Shin; Tae-Hyun Yoon

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Byungcheul Kim

Gyeongnam National University of Science and Technology

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