Kwon-Chil Kang

Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors

Single-electron transistors that have electrical tunneling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room temperature (300 K). Operation characteristics and multioscillation peaks are further investigated at low temperature (80 K). The period of Coulomb oscillation is 2.3 V due to an ultrasmall control gate capacitance, and oscillation peaks are shifted through the side gate bias, which is explained by the derived stability plot for dual-gate structures. Even with the side gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed.

Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure

We have fabricated single-electron transistors (SETs) with a recessed channel structure using a thermal oxidation process for decreasing the size of quantum dots (QDs). Moreover, the QDs are defined on a one-dimensional silicon nanowire by two tunneling barriers induced through thermal oxidation. Also, for decreasing the control gate capacitance, the dimension of the control gate depends not on the electron beam or photolithography method. The control gate is formed by the controllability of chemical vapor deposition (CVD). Owing to this small capacitance, we have clear Coulomb oscillation peaks and negative differential trans-conductance curves at room temperature. The oscillation period of the fabricated device is approximately 1.9 V.

Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications

We have fabricated silicon-based dual-gate single-electron transistors (DG-SETs) with electrically induced tunneling barriers. By utilizing e-beam lithography patterning and additional oxidation process, the device is scaled down beyond the previously demonstrated dual-gate structures. As a result, Coulomb oscillation is maintained in the large control gate bias region and its oscillation period is increased to 2.3 V. Based on the measurement, SET SPICE model is optimized and useful complementary metal–oxide–semiconductor (CMOS)/SET circuits which reduce the current oscillation period or improve peak-to-valley current ratio (PVCR) are investigated by using the model.

Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates

In this paper, we propose a novel self-aligned dual-gate single-electron transistor having nano wire channel and surrounding side gates. By restricting the control gate effect to the top surface of the channel and intensifying the depletion effect through the surrounding side gates, the parasitic metal–oxide–silicon field-effect transistor (MOSFET) current and the quantum dot size are expected to be decreased. These advantages of the proposed structure are investigated through three-dimensional (3D) device simulation. In addition, the devices are fabricated by utilizing the silicon process and their electrical characteristics are analyzed at both room temperature and low temperature. Also, diverse device parameters are extracted from the measurement results, and they are systematically compared.

Higher order kernels in adaptive location estimation

In the semiparametric location model, an adaptive location estimate can be obtained by plugging kernel estimates of density and its derivative into the one-step approximation of the parametric maximum likelihood estimate. In this paper, we investigate the effect of higher order kernels on second order asymptotics of the adaptive location estimate. The optimal order of bandwidths in terms of estimating the location parameter are established. We also give some simulation results to see the effect of higher order kernels for moderate sample sizes.

Investigation of vertical type single-electron transistor with sidewall spacer quantum dot

Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices [1]. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region [2]. However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works [1][3]. Since the smaller QD a SET has, the better operation characteristic it has at room temperature (RT), the characteristic of the SET device can be observed more clearly than previous works with the simple process to downsize a QD.

Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure

In this work, we have fabricated and characterized the dual gate single-electron transistors (DG-SETs). This device has recessed channel and underlapped source/drain structure. Fabrication flow and device structure are described as well as operation schemes. Clear Coulomb oscillation peaks and negative differential trans-conductance curve are observed at room temperature (300 K). Measurement results obtained at period of Coulomb oscillation is 0.9 V due to an ultra-small control gate capacitance, and oscillation peaks are shifted through the sidewall gate bias. Also, in order to confirm that single electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the silicon-on-insulator (SOI) active, room temperature measurement results for device with different parameters is compared.

Fabrication and improved characteristics of self-aligned dual-gate single-electron transistors

Single-electron transistors (SETs) have been expected to become one of the promising devices in future ultra-low power and high-density systems. Especially, silicon based SETs have advantages in the fabrication and design of SET and MOSFET hybrid circuits. Due to its potential, lots of research has been conducted and various structures have been introduced. However, low operation temperature and poor fabrication controllability still remain as main obstacles to widespread utilization. In this respect, dualgate SETs using electrical tunneling barriers have strengths compared to other structures. This is because the height of the tunneling barriers can be controlled through external bias and the quantum dot size is further decreased due to electric field effects. In our research, dual-gate SETs were fabricated with a CMOS compatible and self-aligned process. Process parameters were optimized in order to reduce the total capacitance of a quantum dot, and Coulomb oscillation peak was observed in the roomtemperature operation of the fabricated device.

Room temperature behavior of poly-silicon quantum dot single electron transistors

For room temperature operation and reproducibility of single electron transistors (SETs), we propose a fabrication method of an SET with a self-aligned quantum dot. The quantum dot is formed by the selective etch of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon. The device is named as a PQD-SET, i.e., poly-silicon quantum dot single electron transistor. PQD-SET shows clear Coulomb oscillation at room temperature.

Poly-silicon quantum dot single electron transistors

For room temperature operation and reproducibility of single electron transistors (SETs), we propose a fabrication method of an SET with a self-aligned quantum dot. The quantum dot is formed by selective etch of a silicon nanowire on a planarized surface and subsequent deposition and etch-back of poly-silicon. The device is named as PQD-SET, i.e., poly-silicon quantum dot SET. PQD-SET shows clear Coulomb oscillation at room temperature.