Son Ngoc Truong

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

New Twin Crossbar Architecture of Binary Memristors for Low-Power Image Recognition With Discrete Cosine Transform

In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M+ and M-. Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M+ arrays. With the reduced number of LRS cells in two M+ arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.

Sequential Memristor Crossbar for Neuromorphic Pattern Recognition

Most of humans intelligent behaviors such as inference, prediction, anticipation, etc. are based on the processing of sequential data from humans sensory systems. Thus, a sequential memory that can process sequential information is very essential to mimic brains intelligent behaviors. In this paper, we propose a new sequential memristor crossbar which is regarded as the first memristor circuit that copes with the sequential data. The new crossbar is composed of two layers which are the base layer and the sequential one, respectively. The base layer can recognize only static items one by one. The sequential layer can detect the serial order of items and find the best match with the detected sequence among many reference sequences stored in the memristor array. The new crossbar can recognize the tested sequences of items as well as 88.6% on average for the memristance variation of 0%. The variation tolerance is also tested from 0-% variation to 20-% variation in the proposed sequential crossbar.

Experimental demonstration of sequence recognition of serial memristors

The sequence recognition is very essential in mimicking brain’s neocortical function because most of input patterns to brain’s neocortex are dynamically changing over time, not static regardless of time. In this paper, we experimentally demonstrate the sequence recognition for various input sequences using serial memristors, for the first time. In this experiment, the serial memristors are used, which were fabricated with carbon fiber and aluminum film on glass substrate. To verify the sequence recognition, we store the following 3 sequences in the fabricated serial memristors, which are ‘A’→‘B’→‘C’, ‘B’→‘A’→‘C’, and ‘C’→‘B’→‘A’, respectively. By performing this experiment, it is verified the serial memristors are changed to Low Resistance State only when the input sequence matches the stored one. When the input sequence is different from the stored one, the serial memristors remain unchanged. The simple voltage comparator can be used to sense the output voltage to indicate whether the sequence matching happens or not. This experimental demonstration can be very useful to realize memristor crossbars which can process the temporal and sequential patterns in future.

Memristor circuits and systems for future computing and bio-inspired information processing

Memristors can be used in mimicking synaptic plasticity of biological neuronal systems. In addition, memristor crossbars can be realized in 3-dimensional architecture like human brain. This possibility of 3-dimensional integration is crucial in implementing the full-scale electronic neuron-synapse system in future. One more thing to note here is that memristor-based neuromorphic systems can be more energy-efficient than the conventional Von Neumann ones in some applications such as bio-inspired pattern processing. This is because they are more suitable to brain-like parallel processing. Based on these advantages of memristor-based neuromorphic systems, this paper reviews the memristor logics, where the computation and memory can be merged together. Then, we introduce neuromorphic memristor crossbars which can mimic the brains pattern recognition of speech and image. The simulation results of neuromorphic crossbars strongly highlight the future possibility of memristor circuits in brain-mimicking pattern processing. In Cellular Nanoscale Network (CNN), memristors can be used in analog multiplication that is essential to perform CNN pixel calculation with low power consumption and high-area density.

Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognition

Memristors were mathematically found by L. O. Chua in 1971 and experimentally demonstrated by HP researchers in 2008 [1], [2]. Since then, memristors have been considered suitable for neuromorphic circuits and systems, because they have some similarities with brains neuronal systems [3], [4], [5]. Memristors are possibly 3-dimensioanl, parallel, analog, defective, etc like brains neuronal systems [6], [7]. In spite of these similarities, memristors are fundamentally electronic devices, not biological cells. The difference of electronic devices versus biological cells leads to very distinctive phenomenal gaps which can be stated as follows; externally-designed versus self-organized, externally-programmed versus self-learned, defect-susceptible versus defect-curable, etc.

FPGA-based training and recalling system for memristor synapses

Nanoscale memristors can be used as synapses in brain-mimicking neuromorphic systems. To act as synapses, memristors should be programmed or trained for the target synaptic weight values by applying a sequence of voltage pulses. In this paper, we show an implementation of FPGA-based training and recalling system of memristor synapses. Using the implemented FPGA-based training and recalling system of memristor synapses, we compare various pule modulation schemes which can be used in training and recalling memristor synapses. This comparison tells us that the pulse amplitude modulation is more suitable to train memristor synapses precisely than the others.

Memristor-based cellular nanoscale networks: Theory, circuits, and applications

In this paper, the theory, circuit design, and possible applications of Cellular Nanoscale Networks (CNNs) which are based on memristor technology are reviewed. In the memristor-based CNNs, memristors can be used to realize the analog multiplication circuit that is essential in performing the computation functions of CNNs with low-power consumption and small area. Compared to the memristor-based crossbar architecture that can be used to mimic the fundamental neuron-cell-level operation such as Spike Time Dependent Plasticity (STDP), the memristor-based CNN circuit is more suitable in mimicking the advanced sensory systems such as image processing of humans retina. In this paper, we explain the basics of CNN computation at first and we discuss the previous memristor-based CNN circuits that are very useful in performing analog multiplication. And, also, we think of some practical issues of CNN circuits and discuss the possible solutions. For the CNN applications using memristors, we show the simulation results of CNN circuit with Laplacian template that can be used in the edge detection of various images.

Statistical analysis on variation tolerance of time-shared Twin Memristor Crossbar for pattern matching

In this paper, we analyze the variation tolerance of time-shared Twin Memristor Crossbar (TMC) for various inter-correlation and intra-correlation parameters. Here the percentage variation in memristance is increased from 0% to 40%. The statistical analysis performed here indicates the original TMC and the time-shared TMC show almost the same tolerance to memristance variation when the variation of all memristors in one array are assumed random, referred to as intra-array correlation is zero. However, when the intra-array correlation becomes as high as 1, in other words, variations of all memristors in the same array are correlated each other, the time-shared TMC shows better recognition rate by 5% on average, compared to the original TMC. From the statistical simulation results, we can expect the time-shared TMC has better variation-tolerance than the original TMC, in pattern matching application.