Kyo-Suk Chae

Dependency of anti-ferro-magnetic coupling strength on Ru spacer thickness of [Co/Pd]n-synthetic-anti-ferro-magnetic layer in perpendicular magnetic-tunnel-junctions fabricated on 12-inch TiN electrode wafer

We investigated the Ru spacer-thickness effect on the anti-ferro-magnetic coupling strength (Jex) of a [Co/Pd]n-synthetic-anti-ferro-magnetic layer fabricated with Co2Fe6B2/MgO based perpendicular-magnetic-tunneling-junction spin-valves on 12-in. TiN electrode wafers. Jex peaked at a certain Ru spacer-thickness: specifically, a Jex of 0.78 erg/cm2 at 0.6 nm, satisfying the Jex criteria for realizing the mass production of terra-bit-level perpendicular-spin-transfer-torque magnetic-random-access-memory. Otherwise, Jex rapidly degraded when the Ru spacer-thickness was less than or higher than 0.6 nm. As a result, the allowable Ru thickness variation should be controlled less than 0.12 nm to satisfy the Jex criteria. However, the Ru spacer-thickness did not influence the tunneling-magneto-resistance (TMR) and resistance-area (RA) of the perpendicular-magnetic-tunneling-junction (p-MTJ) spin-valves since the Ru spacer in the synthetic-anti-ferro-magnetic layer mainly affects the anti-ferro-magnetic coupling e...

Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process

We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

Dependency of tunneling magneto-resistance on Fe insertion-layer thickness in Co2Fe6B2/MgO-based magnetic tunneling junctions

For Co2Fe6B2/MgO-based perpendicular magnetic tunneling junctions spin valves with [Co/Pd]n-synthetic-antiferromagnetic (SyAF) layers, the tunneling-magneto-resistance (TMR) ratio strongly depends on the nanoscale Fe insertion-layer thickness (tFe) between the Co2Fe6B2 pinned layer and MgO tunneling barrier. The TMR ratio rapidly increased as tFe increased up to 0.4 nm by improving the crystalline linearity of a MgO tunneling barrier and by suppressing the diffusion of Pd atoms from a [Co/Pd]n-SyAF. However, it abruptly decreased by further increasing tFe in transferring interfacial-perpendicular magnetic anisotropy into the IMA characteristic of the Co2Fe6B2 pinned layer. Thus, the TMR ratio peaked at tFe = 0.4 nm: i.e., 120% at 29 Ωμm2

Electrical Failure Analysis Methodology for DRAM of 80nm era and beyond using Nanoprober Technique

In this paper, the electrical failure analysis for DRAM of design rule as 80 nm and beyond by using nanoprober technique was described. We have successfully measured and evaluated electrical characteristics of periphery and cell array transistors of 80 nm DRAM using nanoprober. Measurements for Metal Contact (MC), Bit Line (BL) and Bit Line Contact (BLC) probing were proceeded and compared with Test Element Group (TEG) probing results. Interconnect Characterization Environment (ICE) simulation was also carried out to verify the current decrease of BLC probing results. Measurement for characteristics of memory cell array transistors, which had 150 nm pitch, of 80 mn DRAM was possible. It is concluded that a direct probing method using the nanoprober technique was an useful tool of the electrical failure analysis for 80 nm DRAM and beyond generations.

Improved evaluation of DRAM transistors and accurate resistance measurement for real chip contacts by nano-probing technique

In this study we have measured and analyzed characteristics of real transistors on dynamic random access memories (DRAM) including cell transistor by using nano-probing system for improved failure analysis. Measuring results of the conventional pad probing and nano-probing were compared on test element group (TEG) patterns of large transistors. The transistor characteristics of nano-probing results were evaluated for the each layer of DRAM structure with comparing the TEGs pad probing results. We also have measured sheet resistance (Rs) and contact resistance (Rc) on source and drain of real transistor bit line contacts (BLC) by nano-probing with transmission line model (TLM) method. We could find the effect of floating BLC was negligible and the effective resistance was only depending on the facing length of the contact plug bottom.