Tae-Hun Shim

Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate

With W/TiN stack gate deposited at high temperature, excellent time-dependent dielectric breakdown (TDDB) characteristics of the gate oxide were obtained in MOS capacitors. In the case of negative gate bias where thin oxide reliability becomes critical, the TiN gate provides a much longer time to breakdown than that of n/sup +/-poly gate due to a larger barrier height and less F-N tunneling current. In spite of skipping the conventional reoxidation process, a breakdown field larger than 10 MV/cm could be obtained in MOS transistors by undercutting TiN with boiling H/sub 2/SO/sub 4/. With a double spacer and undercutting scheme, the short channel effect of NMOS and PMOS transistors could be suppressed up to L/sub gate//spl sim/0.3 /spl mu/m.

Effects of Pt capping layer on perpendicular magnet anisotropy in pseudo-spin valves of Ta/CoFeB/MgO/CoFeB/Pt magnetic-tunneling junctions

We investigated how the Pt capping layer affected perpendicular magnet anisotropy in magnetic-tunnel-junctions fabricated with a Ta electrode, a lower CoFeB layer, an MgO barrier, an upper CoFeB layer, and a Pt capping electrode, which was estimated by using an anisotropy constant multiplied by the upper CoFeB layer thickness (Ku * t). The maximum Ku * t was found at an annealing temperature of 300 °C for an magnetic tunnel junction with an upper CoFeB layer thickness of 0.9 nm, indicating a highly textured MgO (100) barrier of 1.0 nm with none of the remaining Pt inter-diffused in the upper CoFeB layer.

Co2Fe6B2/MgO-based perpendicular spin-transfer-torque magnetic-tunnel-junction spin-valve without [Co/Pt] n lower synthetic-antiferromagnetic layer.

We design a Co2Fe6B2/MgO-based p-MTJ spin-valve without a [Co/Pt] n lower synthetic-antiferromagnetic (SyAF) layer to greatly reduce the 12-inch wafer fabrication cost of the p-MTJ spin-valve. This spin-valve achieve a tunneling magnetoresistance (TMR) of 158% and an exchange field (H ex) of 1.4 kOe at an ex situ annealing temperature of >350 °C, which ensures writing error immunity. In particular, the TMR ratio strongly depends on the body-center-cubic capping-layer nanoscale thickness (t bcc), i.e., the TMR ratio peaks at t bcc = 0.6 nm.

Dependency of anti-ferro-magnetic coupling strength on Ru spacer thickness of [Co/Pd]n-synthetic-anti-ferro-magnetic layer in perpendicular magnetic-tunnel-junctions fabricated on 12-inch TiN electrode wafer

We investigated the Ru spacer-thickness effect on the anti-ferro-magnetic coupling strength (Jex) of a [Co/Pd]n-synthetic-anti-ferro-magnetic layer fabricated with Co2Fe6B2/MgO based perpendicular-magnetic-tunneling-junction spin-valves on 12-in. TiN electrode wafers. Jex peaked at a certain Ru spacer-thickness: specifically, a Jex of 0.78 erg/cm2 at 0.6 nm, satisfying the Jex criteria for realizing the mass production of terra-bit-level perpendicular-spin-transfer-torque magnetic-random-access-memory. Otherwise, Jex rapidly degraded when the Ru spacer-thickness was less than or higher than 0.6 nm. As a result, the allowable Ru thickness variation should be controlled less than 0.12 nm to satisfy the Jex criteria. However, the Ru spacer-thickness did not influence the tunneling-magneto-resistance (TMR) and resistance-area (RA) of the perpendicular-magnetic-tunneling-junction (p-MTJ) spin-valves since the Ru spacer in the synthetic-anti-ferro-magnetic layer mainly affects the anti-ferro-magnetic coupling e...

Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process

We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

Impact of the top silicon thickness on phonon-limited electron mobility in (110)-oriented ultrathin-body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

We investigated through a theoretical simulation how the phonon-limited electron mobility in both (110)- and (100)-oriented ultrathin-body (UTB) silicon-on-insulator (SOI) n-metal-oxide-semiconductor field-effect transistors (MOSFETs) depends on the top silicon thickness within a range from 20to2nm. No electron mobility enhancement was observed in (110) UTB SOI n-MOSFETs when the top silicon thickness was around 5nm, unlike in (100) UTB n-MOSFETs. Thus, electron mobility in (110) UTB SOI n-MOSFETs decreased with top silicon thickness, particularly in the range below 10nm. We attributed the electron mobility degradation in (110) UTB SOI n-MOSFETs within the top silicon thickness range below 10nm to a decrease in the effective width of the inversion layer and an increase in intravalley acoustic phonon scattering, rather than to less carrier repopulation due to less band splitting between two- and fourfold valleys.

The effect of donor layer thickness on the power conversion efficiency of organic photovoltaic devices fabricated with a double small-molecular layer

In organic photovoltaic (OPV) devices fabricated with a double small-molecular layer, the power conversion efficiency strongly depends on the thickness of the organic donor layer (here, copper phthalocyanine). In other words, the power conversion efficiency increases with the donor layer thickness up to a specific thickness ( approximately 12.7 nm) and then decreases beyond that thickness. This trend is associated with the light absorption and carrier transport resistance of the small-molecular donor layer, both of which strongly depend on the layer thickness. Experimental and calculated results showed that the short-circuit current due to light absorption increased with the donor layer thickness, while that due to current through the donor layer decreased with 1/R. Since the total short-circuit current is the product of the light absorption current and current through the donor layer, there is a trade-off, and the maximum power conversion efficiency occurs at a specific organic donor layer thickness (e.g. approximately 12.7 nm in this experiment).

Comparative study of self-heating effect on electron mobility in nano-scale strained silicon-on-insulator and strained silicon grown on relaxed SiGe-on-insulator n-metal–oxide–semiconductor field-effect transistors

From the viewpoint of the silicon thickness limit for mobility enhancement in a strained Si channel, we investigated the difference in the self-heating effect on electron mobility between strained silicon-on-insulator (sSOI) and strained Si grown on relaxed SiGe-on-insulator (e-Si SGOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) as a function of silicon thickness. We found, for the first time, by numerical simulation that when considered with the presence of self-heating in the silicon thickness range from 5 to 10 nm, the reduction in the mobility enhancement ratio of sSOI n-MOSFETs is less than that of e-Si SGOI n-MOSFETs by numerical simulation. In addition, we confirmed that the quantum size effect, occurring at the peak mobility value of a 3 nm silicon thickness, disappeared in sSOI n-MOSFETs but was suppressed in e-Si SGOI n-MOSFETs. Therefore, we propose that an sSOI n-MOSFET is a more promising device than a e-Si SGOI n-MOSFET for high-performance devices with a design rule of less than 45 nm.

Dependence of memory margin of Cap-less memory cells on top Si thickness

We investigated the dependence of Cap-less memory on top of silicon with a thickness between 15.5 and 72.3 nm. It was confirmed that the memory margin depends on the impact ionization rate associated with the increased conduction current density and the decreased lateral electric field as the top silicon thickness increases. In particular, we observed that the maximum memory margin is 61 μA at a 45 nm top silicon thickness, where the impact ionization rate is maximized. Consequently, we obtained the optimal top silicon thickness of 45 nm for Cap-less memory cells operating in fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors.

Dependence of temperature and self-heating on electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

We investigated the dependence of temperature and self-heating on electron mobility in ultrathin body fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors as a function of silicon thickness by analyzing their electron states and electrical characteristics. We found that as the temperature increases, electron mobility decreases regardless of the silicon thickness. We also found that there is a less decrease when the silicon thickness is less than 3 nm than when it is greater than 3 nm. This is because there is a greater electron occupancy in a twofold valley. We demonstrated that the quantum size-effect, i.e., the higher electron mobility in silicon with a thickness less than 3 nm caused by the size-effect, can be eliminated by self-heating.