Kyong Taek Lee

PBTI-Associated High-Temperature Hot Carrier Degradation of nMOSFETs With Metal-Gate/High-

Due to the increased physical dielectric thickness and reduced gate leakage in metal-gate/high-k devices, degradation caused by channel hot carriers (HCs) becomes more significant than positive bias temperature stress. In an analysis of metal-gate/high-k devices, accelerated channel HCs were found to induce permanent interface damage. Moreover, the overall threshold voltage shifts caused by HC stress were enhanced at higher temperatures, which is due to an association with positive bias temperature instability. Therefore, high-temperature HC stress has emerged as a dominant degradation factor in short-channel nMOSFETs with metal-gate/high-k dielectrics.

k

The effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related effects, device characteristics under mechanical-bending stress and stressor layers were compared. The compressive-stressor device exhibits improved initial interface quality, although slightly degraded reliability characteristics, due to an increased hydrogen passivation of the dielectric/substrate interface. Thereby, the hydrogen passivation in the interface is found to be the primary cause of the difference in reliability characteristics.

Dielectrics

Low-frequency noise (LFN) after channel soft oxide breakdown (SBD) of n-MOSFETs with a HfLaSiO gate dielectric and TaN metal gate shows a Lorentzian-like spectrum, which is not observed in HfSiO gate dielectric devices after channel SBD. This is related to the spatial location of the SBD spot. Because La weakens atomic bonding in the interface layer, the SBD spot is generated close to the Si/SiO2 interface. This is verified by using time domain analysis. To examine the property of this Lorentzian-like noise, LFNs after channel SBD are measured repeatedly after arbitrary times. After about 20 h, LFN finally shows an increase only at the low-frequency part of the noise spectrum (f < 1 kHz). These results suggest that the trap distribution after arbitrary times spreads instead of remaining localized. Therefore, the traps or the La-O defect clusters have severe unstable distribution and induce an increase of the localized field, which, in turn, causes the traps to percolate through the high-k dielectric.

A Study of Strain Engineering Using CESL Stressor on Reliability Comparing Effect of Intrinsic Mechanical Stress

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric

We investigate RF performances and hot carrier effects of nMOSFETs at cryogenic temperature. RF performances of HfO<inf>2</inf> dielectric nMOSFET at 77 K are improved more than those of SiO<inf>2</inf> dielectric nMOSFET although DC performances are improved similarly. The nMOSFET with HfO<inf>2</inf> dielectric has 127.4 GHz f<inf>T</inf> and 75.4 GHz f<inf>max</inf> at 77 K. In hot carrier injection measurement, g<inf>m</inf> of HfO<inf>2</inf> nMOSFET at 77 K is degraded more than 300 K although V<inf>th</inf> shift is less. The cause of g<inf>m</inf> reduction is discussed related to the trapping.

The Effect of a Si Capping Layer on RF Characteristics of High-

We have investigated reliability characteristics for a high-k/metal gate MOSFET with strain engineering under constant voltage stress (CVS). Using contact edge stop layer (CESL), tensile and compressive strains are applied to the channel region. Since the compressive MOSFET has more hydrogen in the CESL, the MOSFET has lower reliability characteristics than others. Though the hydrogen can passivate dangling bonds in the high-k dielectric, the passivated bonds are easily broken by voltage stress, which cause degradation of high-k layer.

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We present high pressure hydrogen annel (HPHA) effects in two types contact etch stop layer (CESL) nitride MOSFETs. Performances increased in both samples of using rapid thermal chemical vapor deposition (RTCVD) and plasma enhanced chemical vapor deposition (PECVD) nitride stress layers, but reliability only degraded in PECVD samples after HPHA.

/Metal Gate SiGe Channel pMOSFETs

Effects of high pressure hydrogen annealing (HPHA) process on a nitride contact etch stop layer (CESL) MOSFETs is studied. High interface quality by HPHA leads to improved on-current (Ion) and transconductance (Gm) while reliability degradation is acceptable.

RF and hot carrier effects in metal gate/high-k dielectric nMOSFETs at cryogenic temperature

RF performances of 100-nm metal gate/high-k dielectric nMOSFET and parameters degradation by hot carrier injection to apply to RF integrated circuits are investigated. The attained nMOSFETs RF performances are 132-GHz f<inf>T</inf> and 44-GHz f<inf>max</inf>. In addition to RF figures of merit (FOM, f<inf>T</inf> and f<inf>max</inf>), variation of capacitance and resistance is monitored to study hot carrier effects.

Reliability of HFO 2 /SIO 2 dielectric with strain engineering using CESL stressor

Test structures for accurate UHF capacitance-voltage (C-V) measurements of high performance CMOSFETs with Hf-based high-k dielectric and TiN metal gate are analyzed. It is shown that series resistance or substrate resistance between the channel region and body contact plays a role in UHF C-V measurements. The substrate resistance beneath the gate region also impacts accurate UHF C-V measurements. Therefore, minimization of series resistance through short gate lengths with a minimum distance between the source/drain and body contact is highly desired for an accurate evaluation of gate dielectric thickness using UHF C-V measurements.