Gil-Bok Choi

Low-Temperature Performance of Nanoscale MOSFET for Deep-Space RF Applications

RF characteristics of a nanoscale MOSFET are measured and analyzed at temperatures ranging from 4.2 to 300 K for deep-space RF applications. This device shows a 197-GHz current gain cutoff frequency (fT) and a 162-GHz maximum oscillation frequency (fmax) when operating at liquid-helium temperature, which represent a 60% and 80% improvement compared to room temperature performances, respectively, fT continually improves as the temperature decreases to near-liquid-helium temperature due to the decrease of gate capacitance (Cgg). fmax decreases as the temperature is lowered below 25 K due to the increase of gate resistance (Rg).

Analysis of Contact Effects in Inverted-Staggered Organic Thin-Film Transistors Based on Anisotropic Conduction

In this paper, we propose an analytic model for inverted-staggered organic thin-film transistors, and we use the proposed model to investigate the dependence of contact effect on the voltage bias, the film thickness of the organic semiconductor, and the channel length. In our model, the variable-range-hopping transport is adopted for the conduction in the horizontal direction to the semiconductor-insulator interface, and the space-charge-limited conduction is adopted for the conduction in the vertical direction by considering the molecular orientations. Qualitative agreement is obtained between simulation and measurement in the steady-state characteristics. From simulation study, we notice that the contact resistances vary with the source-gate voltage and with the source-drain voltage, the film thickness requires to be optimized to improve the on-current and the linearity in the linear operating regime, and the overlap length between the gate electrode and the source/drain contact needs to be guaranteed for the short-channel devices because it would not be scaled as much as the channel length.

On the RF Series Resistance Extraction of Nanoscale MOSFETs

A new extraction method of series resistance based on the radio frequency S-parameter measurement for sub -0.1 mum metal oxide semiconductor field-effect transistor is presented. The practical limit of conventional methods is analyzed from measurement and simulation. From this analysis, analytical expressions are derived, and linear regression techniques are used to extract the series resistances. The proposed method improves the accuracy and reduces the measurement frequency.

RF Capacitance Extraction Utilizing a Series Resistance Deembedding Scheme for Ultraleaky MOS Devices

An accurate extraction method for series resistance and capacitance based on RF S-parameter measurement in ultraleaky MOS devices is presented in this paper. The method is proven by using a three-element equivalent circuit model for a capacitor and a well-known microwave theory. The proposed method improves the measurement accuracy and significantly reduces the frequency-dependence of capacitance. This method is demonstrated for a 1.5 nm SiO2 dielectric NMOSFET.

A New Physical

In this letter, a new physical 1/f noise model is developed for double-stack high-k dielectric MOSFETs. This new model modifies the trapping-time-constant term in multistack unified noise model. Conventional 1/f noise model is built on the simple square potential approximation which did not account the electric field dependence on trapping time constant. The new model takes into account of a resultant tunneling process from the actual sloped potential in order to eliminate the discrepancies of dielectric trap density on the dielectric thickness and the gate bias. Our model successfully predicts 1/f noise data obtained from SiO2/HfO2 double-stack high- k devices with various gate-dielectric thicknesses using a single set of modeling parameter.

\hbox{1}/f

In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, Sid, for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.

Noise Model for Double-Stack High-

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

k

In this paper, a novel method for effective mobility extraction of the advanced MOSFET devices using RF modeling scheme is proposed. The proposed method is robust to high gate leakage current and parasitic source/drain resistance. Also, this method can substantially reduce error from drain bias mismatch between channel conductance and gate-to-channel capacitance measurement, uses only single device, and is applicable to small-area devices. nMOSFET with HfSiON gate dielectric and TiN gate electrode is demonstrated with the proposed method.

Gate-Dielectric MOSFETs

We investigate RF performances and hot carrier effects of nMOSFETs at cryogenic temperature. RF performances of HfO<inf>2</inf> dielectric nMOSFET at 77 K are improved more than those of SiO<inf>2</inf> dielectric nMOSFET although DC performances are improved similarly. The nMOSFET with HfO<inf>2</inf> dielectric has 127.4 GHz f<inf>T</inf> and 75.4 GHz f<inf>max</inf> at 77 K. In hot carrier injection measurement, g<inf>m</inf> of HfO<inf>2</inf> nMOSFET at 77 K is degraded more than 300 K although V<inf>th</inf> shift is less. The cause of g<inf>m</inf> reduction is discussed related to the trapping.

Characterization of Gate-All-Around Si-NWFET, including R sd , cylindrical coordinate based 1/f noise and hot carrier effects

RF performances of 100-nm metal gate/high-k dielectric nMOSFET and parameters degradation by hot carrier injection to apply to RF integrated circuits are investigated. The attained nMOSFETs RF performances are 132-GHz f<inf>T</inf> and 44-GHz f<inf>max</inf>. In addition to RF figures of merit (FOM, f<inf>T</inf> and f<inf>max</inf>), variation of capacitance and resistance is monitored to study hot carrier effects.