Joo Tae Moon

Electrical observations of filamentary conductions for the resistive memory switching in NiO films

Experimental results on the bistable resistive memory switching in submicron sized NiO memory cells are presented. By using a current-bias method, intermediate resistance states and anomalous resistance fluctuations between resistance states are observed during the resistive transition from high resistance state to low resistance state. They are interpreted to be associated with filamentary conducting paths with their formation and rupture for the memory switching origin in NiO. The experimental results are discussed on the basis of filamentary conductions in consideration of local Joule heating effect.

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Improvement of resistive memory switching in NiO using IrO2

For the development of resistive memory devices using NiO, improvements of several memory switching properties are required. In NiO memory cells with noble metal electrodes, broad dispersions of memory switching parameters are generally observed with continuous memory switchings. We report the improvements in minimizing the dispersions of all memory switching parameters using thin IrO2 layers between NiO and electrodes. The role of thin IrO2 layers on NiO growth and memory switching stabilization are discussed.

An edge contact type cell for Phase Change RAM featuring very low power consumption

In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Al2O3 nanotubes and nanorods fabricated by coating and filling of carbon nanotubes with atomic-layer deposition

Aluminum oxide (Al2O3) nanotubes and nanorods were fabricated by coating and filling of multiwalled carbon nanotubes (MWNTs) with atomic-layer deposition (ALD). Al2O3 material was deposited on the MWNTs at a substrate temperature of 300°C using trimethylaluminum and distilled water. Transmission electron microscopy, high resolution transmission electron microscopy, energy-dispersive X-ray spectroscopy, and selected area electron diffraction of the deposited MWNTs revealed that amorphous Al2O3 material coats the MWNTs conformally and that this material fills the inside of the MWNTs. These illustrate that ALD has an excellent capability to coat and fill any three-dimensional shapes of MWNTs conformally without producing any crystallites.

High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier

For the first time, a nitride/oxide/nitride stacked tunnel structure is adopted as highly field-sensitive tunnel barrier to improve both program/erase speed and data retention of nanocrystal memory. Product-adaptive nonvolatility (>10 years at 85/spl deg/C) and cycling endurance (>10/sup 6/) were obtained with the program time of 10 /spl mu/s at V/sub G/=8 V and the erase time of 100 /spl mu/s at V/sub G/=-8 V with 0.84 V threshold window. The program speed was 100 times faster and the voltage was about 10 V smaller than those of a conventional NAND type flash memory cell. These results strongly suggest that nanocrystal floating gate memory becomes a promising solution to overcome the scaling limitation of the conventional floating gate memory cell.

Sub-0.1 μm nitride hard mask open process without precuring the ArF photoresist

A nitride hard mask open process with an ArF photoresist (PR) has been achieved in a dual-frequency capacitively coupled plasma-type reactor to pattern 200 nm high and 90 nm wide nitride lines. It was found that the most serious problems of the hard mask open process with ArF PR are striation and wiggling of the PR. Striation is a serious side roughness of nitride lines that results from the deformation of the top portion of the PR during dry etching. This striation is aggravated by the high ion energy and the low selectivity of the nitride to the PR. Wiggling of the PR is defined as the collapse of the PR resulting from slimming of the ArF PR and deposition of a fluorocarbon polymer during dry etching. The wiggling of the PR is strongly dependent on the conditions of the dry etching, such as chamber pressure, chiller temperature, gas chemistry, and total etch time, all of which determine the temperature of the top surface of the ArF PR during dry etching. With the help of plasma diagnostics and an unders...

Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.

Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation

first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge2Sb2Te5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.