Kyuchul Chong

High-performance on-chip transformers

To study the substrate effect on transformer performance, several types of spiral transformers were fabricated on p/sup +/ silicon substrate with microporous silicon (PS) regions. Our analysis shows that the use of PS significantly reduces the substrate effects including eddy current and capacitive coupling between spirals and the substrate. The reduced substrate effects lead to higher Q-factor and resonant frequency (f/sub r/), mutual reactive coupling coefficients (k/sub Im/) with larger useable band width and higher available gain (G/sub a/) mainly because of the reduction in power loss to the substrate. The use of PS can greatly increase transformer performances and broaden the parameter space for on-chip transformer layout optimization.

High-performance inductors integrated on porous silicon

To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p/sup -/ and p/sup +/ silicon substrate. /spl pi/-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher Q-factor and resonant frequency (f/sub r/) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in Q-factor and f/sub r/. Similarly, much higher Q-factor can be obtained for reasonable inductance and f/sub r/.

A porous Si based novel isolation technology for mixed-signal integrated circuits

A novel isolation technology for RF applications based on semi-insulating porous Si (PS) is demonstrated. RF cross-talk isolation of 70 dB at 2 GHz and -45 dB at 8 GHz has been demonstrated using PS trenches that provide complete isolation between neighboring regions of a p/sup +/ Si chip. On-chip spiral inductors of 6 nH fabricated over the PS regions have been demonstrated with Q/sub max/ /spl sim/29 at 7 GHz and a resonant frequency of over 20 GHz.

Low capacitance and high isolation bond pad for high-frequency RFICs

A bond pad structure using semi-insulating porous silicon (PS) is proposed for the purpose of reducing the parasitic pad capacitance and increasing the crosstalk isolation characteristics on low resistivity p/sup -//p/sup +/ epi substrates for high-performance CMOS. Our results show that reducing the parasitic pad capacitance by using PS results in a high bond pad resonant frequency of up to 56.2 GHz (assuming wire bond inductance is 2 nH). In addition, the crosstalk reduction is as much as 6/spl sim/31 dB at frequencies up to 40 GHz even when compared to that on conventional p/sup -/ bulk substrate. Such a high-performance bonding pad structure is important for high-frequency RFICs which require high operation frequency and low substrate effect.

Study of the cross-sectional profile in selective formation of porous silicon

Porous Si is the semi-insulating state of Si, with low thermal expansion mismatch with bulk Si. As a result, it is an excellent material for crosstalk isolation in mixed-signal integrated circuits. We study the formation of isolated porous Si regions in p−-type and p+-type Si substrates with emphasis on the cross-sectional profile of the porous regions. Our study reveals that in addition to the primary undercut due to the isotropic nature of the anodization process, there exists a secondary undercut that is similar in shape to the bird’s beak commonly observed at the edge of field oxides in conventional Si complementary-metal-oxide-semiconductor process. The shape and the extent of the secondary undercut are dependent on the type of mask materials used during selective formation of porous Si as well as the substrate resistivity. The combined experimental and simulation studies pointed to two likely origins of secondary undercuts: the weak adhesion of some of the mask materials and current crowding in bulk...

The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p/sup -/ Si substrate

Locally incorporated porous Si (PS) trenches are used for radio frequency (RF) crosstalk isolation through p/sup -/ Si substrates. PS trenches provide large dielectric separation (large impedance) between the noise producing and the noise sensitive circuits without prohibitively high stress from a thermal expansion coefficient mismatch between bulk Si and the common dielectrics, e.g. SiO/sub 2/ and Si/sub 3/N/sub 4/. A variety of commonly used RF isolation structures are fabricated and compared. The best isolation structure for the p/sup

Study of Ni Metallization in Macroporous Si Using Wet Chemistry for Radio Frequency Cross-Talk Isolation in Mixed Signal Integrated Circuits

/substrates is shown to be the one with p/sup +/ grounding stripes in addition to a PS trench. Crosstalk between Al pads with 800 /spl mu/m separation is reduced to the level comparable to that through air. It is shown that contrary to our previous result using PS trenches in p/sup +/ substrates, p/sup +/ grounding stripes or PS trenches alone is quite ineffective. Superior RF isolation is achieved only when the two approaches are used in conjunction with one another. The combined approach results in additional crosstalk reduction of 21 dB at 2 GHz and 11 dB at 20 GHz.

The promising role of porous Si in mixed-signal integrated circuit technology

A highly conductive moat or Faraday cage of through-the-wafer thickness in Si substrate was proposed to be effective in shielding electromagnetic interference thereby reducing radio frequency (RF) cross-talk in high performance mixed signal integrated circuits. Such a structure was realized by metallization of selected ultra-high-aspect-ratio macroporous regions that were electrochemically etched in p− Si substrates. The metallization process was conducted by means of wet chemistry in an alkaline aqueous solution containing Ni2+ without reducing agent. It is found that at elevated temperature during immersion, Ni2+ was rapidly reduced and deposited into macroporous Si and a conformal metallization of the macropore sidewalls was obtained in a way that the entire porous Si framework was converted to Ni. A conductive moat was as a result incorporated into p− Si substrate. The experimentally measured reduction of crosstalk in this structure is 5~18 dB at frequencies up to 35 GHz.