Daquan Huang

324GHz CMOS Frequency Generator Using Linear Superposition Technique

This paper presents CMOS for terahertz applications, substantially extended the operation range of deep-submicron CMOS by using a linear superposition method, in which we have realized a 324GHz frequency generator in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction

An on-chip resonator with artificial dielectric in place of the LC tank yields reduced metal/substrate losses, higher resonator Q and alambda/4 length reduction of 4.7 times. The VCO uses 90nm CMOS, with 0.015mm2 area, consumes 1.9mW and has a measured phase noise of -100dBc/Hz at 1MHz offset. The FOM is -193dBc/Hz

High-performance inductors integrated on porous silicon

To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p/sup -/ and p/sup +/ silicon substrate. /spl pi/-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher Q-factor and resonant frequency (f/sub r/) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in Q-factor and f/sub r/. Similarly, much higher Q-factor can be obtained for reasonable inductance and f/sub r/.

Millimeter-wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs

Digital control of the effective dielectric constant of a differential mode transmission line is shown up to 60GHz in standard CMOS technology. The effective dielectric constant is shown to increase from 5 to over 50 for the fixed artificial dielectric case. The digital controlled artificial dielectric transmission line (DiCAD) uses MOS switches to dynamically control the phase. DiCAD achieves 50% of the physically available tuning range with effective dielectric constants varying between 7 and 28. Measured results favorably agree with full-wave electromagnetic simulations.

A 60GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity

A compact 60GHz CMOS differential direct conversion receiver front-end based on eight-metal-layer interleaved on-chip transformers is realized for low voltage (1.2V) and high gain (24dB) operation with input 1dB compression point of -11dBm, noise figure of 10.5 dB and power consumption of 4.3mW/arm. Compared with prior arts in CMOS, this receiver achieves the highest gain without an output buffer, highest linearity, lowest noise, and lowest power consumption with smallest die area of 0.022mm2

Three-dimensional impedance engineering for mixed-signal system-on-chip applications

An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p-/p+ Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency

Impact of CMOS Scaling on RF/MMIC Designs

Recent performance advancement in super-scaled CMOS technologies has opened new avenues for implementing RF/MMICs on cost-effective mainstream silicon substrate. This talk addresses critical issues involved in designing those high-frequency circuits under technology constraints of decreasing supply voltage and device gain, increasing device mismatch and metal & substrate losses. The talk will also discuss possible circuit level solutions in both topology and signaling, which may mitigate those constraints and deliver demanded performance and functions for future high frequency communication systems.

A phase-coherent transformer enabled 2:1 frequency divider with 7dB phase noise reduction and speed/spl times/gain/power F.O.M. of 2/spl times/10 (pico-Joule)/sup -1/

This paper demonstrates a phase-coherent transformer (PCT) enabled 2:1 22GHz frequency divider in 0.18 /spl mu/m CMOS with 16 dB power gain and 7dB phase noise reduction. The PCT reverberates magnetic energy between the sensing and latching stages, resulting in extremely power efficient divider circuit topology. High division gain eliminates the use of consecutive buffer amplifiers. Consequently, the PCT divider enjoys low phase noise, low power consumption with a speed/spl times/gain/power F.O.M. of 2/spl times/10/sup 2/ (pico-Joule)/sup -1/.

A phase-coherent transformer enabled 2:1 frequency divider with 7dB phase noise reduction and speed-gain/power F.O.M. of 2x10/sup 2/ (pico-joule)

This paper demonstrates a phase-coherent transformer (PCT) enabled 2:1 22GHz frequency divider in 0.18 /spl mu/m CMOS with 16 dB power gain and 7dB phase noise reduction. The PCT reverberates magnetic energy between the sensing and latching stages, resulting in extremely power efficient divider circuit topology. High division gain eliminates the use of consecutive buffer amplifiers. Consequently, the PCT divider enjoys low phase noise, low power consumption with a speed/spl times/gain/power F.O.M. of 2/spl times/10/sup 2/ (pico-Joule)/sup -1/.