Kyung-hoon Kim

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of ~10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.

A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project utilizes a CML clocking scheme.

A floating tap termination scheme with inverted DBI AC and floating tap forcing technique for high-speed low-power signaling

This paper presents a novel floating tap termination (FTT) scheme with inverted data bus inversion (iDBI_AC) and floating tap forcing (FTF) to remove the DC current path, leading to reduction of static current. The iDBI_AC and FTF are proposed to resolve common-mode stabilization issues for the floating tap termination scheme during transmitting unbalanced data patterns. Power efficiency with the proposed scheme using 0.6V I/O supply and a 0.13-um technology is measured as 0.127mW/Gbps/pin, which is 61% lower than that of a low tap termination (LTT) scheme used in LPDDR4X. In addition to the power benefit, measurement results present that the proposed scheme leads to achieve 7Gbps data-rate without penalty of signal integrity issues and the iDBI_AC minimizes inter-symbol interference (ISI).