Yong-ki Kim

Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F2.

A fast GDDR5 read CRC calculation circuit with read DBI operation

The GDDR5 provides cyclic redundancy check (CRC) function to ensure a high speed operation. The GDDR5 calculates the CRC with read data and transmits the results on error detection code (EDC) pins. This paper presents a scheme to reduce calculation time of CRC when the read data bus inversion (DBI) is enabled. This scheme is applied to GDDR5 product manufactured in 66 nm CMOS process technology and its bandwidth is measured to be greater than 4.0 Gbps on the electric field test.

Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement

A PRAM write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 k Ω, and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times, and the total write-throughput is increased. The rise time is reduced consistently for all levels of the target-current by the auto-scaling effect. Therefore, cell heating control becomes more linear in program-and-verify (PNV) operation. Due to its simple adding-on structure, it is easily compatible with a conventional write driver. A prototype chip was implemented using a 0.18- μm CMOS process. It is also applicable to smaller-scale technology.

A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project utilizes a CML clocking scheme.