Hae-Kang Jung

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

A serpentine guard trace is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The vertical sections of the serpentine guard increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. Comparison with the no guard, the conventional guard, and the via-stitch guard shows that the serpentine guard gives the smallest values in both the peak far-end crosstalk voltage and the timing jitter. The time domain reflectometer (TDR) measurement shows that the peak far-end crosstalk voltage of serpentine guard is reduced to 44% of that of no guard. The eye diagram measurement of pseudo random binary sequence (PRBS) data shows that the timing jitter is also reduced to 40% of that of no guard.

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

By using the data timing control at the transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 3-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The measurement shows that the proposed TX reduces the RX jitters by about 30 ps (more than 50% of the added jitter due to CIJ and ISI) at the data rates from 2.6 Gb/s to 4.0 Gb/s. The proposed scheme can be applied to more than three parallel microstrip lines.

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Serpentine microstrip lines are proposed to eliminate the far-end crosstalk in parallel high-speed interfaces by increasing the capacitive coupling ratio to equal the inductive coupling ratio. Zero far-end crosstalk voltage waveform and zero crosstalk-induced jitter (CIJ) were achieved on an FR4 printed circuit board, by adjusting the unit section length of the serpentine structure. Application of the proposed serpentine microstrip lines to the 2-drop stub series terminated logic DRAM channel increased the maximum data rate from 0.9 to 1.4 Gb/s and reduced CIJ by ~ 78 ps at 3.3 Gb/s.

A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines

A single-ended transmitter eliminates the crosstalk-induced jitter at receiver by controlling the slew rates of the signal at transmitter for the even and odd modes of two parallel coupled microstrip lines. The transmitter chip in a 0.18 µm CMOS process reduces the total RX jitter by about 38 ps (53%) for the data rates from 2.6 to 5 Gbps, and increases the horizontal eye-opening (BER < 1E-12) by about 21% at 5 Gbps.

A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors’ prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The d elayblock generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a 0.18 ㎛ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors’ prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40%

A serpentine guard trace located between two microstrip transmission lines reduced the peak far-end crosstalk voltage and the difference in propagation delay times between the even and odd mode signals by more than half of those of the no guard case, respectively, without the PCB area overhead. This reduction was achieved by increasing mutual capacitance without changing mutual inductance.

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm 2.

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

A single-ended transmitter (Tx) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by subtracting a mimicked crosstalk waveform from data signal at Tx during the data transition time, depending on the data transition of an adjacent line. Since the CIJ component is proportional to the time derivative of data signal, the mimicked crosstalk waveform subtracted at Tx cancels the CIJ at receiver (Rx) for the linearly changing data signal with time. As a by-product, this scheme reduces ISI at Rx. The Tx chip in a 0.13-μm CMOS process reduces the total Rx jitter by 96 ps (69%) at 7.2 Gbps (4-in channels) and by 120 ps (72%) at 6 Gbps (8-in channels).

Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface

The transient far-end crosstalk voltage and the crosstalk-induced jitter of dual in-line memory module (DIMM) connectors are reduced by about 80% by increasing the mutual capacitance between DIMM connector pins with the additional interdigitated-comb-shaped metal-stub patterns on the motherboard. It was confirmed by the far-end crosstalk voltage waveform measurements using TDR and the eye diagram measurements at the data rates of 15 Mbps, 100 Mbps, and 3 Gbps. This reduction technique can be applied to the connectors where the inductive coupling ratio is larger than the capacitive coupling ratio.