Taek-Sang Song

A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network

In this paper, we present a receiver front-end and a frequency source suitable for wireless sensor network applications, in which power consumption is severely restricted under several milliwatts. For such an extremely low-power receiver, current-reusing and frequency multiplying schemes are proposed for both the RF front-end and frequency source. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at the 10-MHz intermediate frequency (IF), taking only 500-muA bias current from a 1.0-V supply voltage. The measured phase noise of the fabricated frequency source is -115.83 dBc/Hz at 1 MHz offset from a 2.2-GHz center frequency, taking 840 muA from a 0.7-V supply. The front-end performance is compared with the previously reported low-power front-ends operating in similar frequency ranges

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme and Duty-Training Circuit (DTC) is presented. A Low Voltage-Swing Terminated Logic (LVSTL) driver using 4-to-1 multiplexer is implemented to the transmitter. A DTC to adjust the CK duty is implemented to the receiver. In addition, a ZQ calibration scheme for Multi-VOH level is also presented. Designed schemes are compatible with the LPDDR4 standard. Power efficiency for the I/O interface is about 2.3mW/Gb/s/pin with 1.1V supply in 2y-nm DRAM process, which is 31% lower than that of LPDDR3.

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

A 16.8 Gbps/channel single-ended transceiver for SiP-based DRAM interface on silicon carrier channel is proposed in this paper. A transmitter, receiver, and channel are all included in a single package as SiP. A current mode 4:1 MUX with 1-tap feed-forward equalizer (FFE) is used as a serializer, and this 4:1 MUX uses 25% duty clock to prevent short circuit current when consecutive 2-phase clocks overlap. Additionally, an open drain output driver with asynchronous type 1-tap FFE is used in the transmitter. Because of its small physical size, a common mode variation of Si-carrier channel from process variation is more serious than that of conventional PCB. This common mode variation degrades bit error rates (BER) at single-ended signaling. To obtain effective single-ended signaling on Si-carrier channel, a source follower-based continuous time linear equalizers and self- VREF generator with training algorithm on the receiver are proposed. An implemented Si-carrier channel uses meshed layer as a reference to reduce insertion loss. A BER less than 1e-12 is achieved in 65 nm CMOS and the power efficiency of the transceiver is 5.9 pJ/bit with 120 Ω terminations at each transceiver side.

A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel

A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.