Kyung-Moon Kim

The viability of anisotropic conductive film (ACF) as a flip chip interconnection technology

The use of anisotropic conductive film (ACF) to form the interconnection between the die and the substrate is one potential variation of flip chip technology. Its appeal comes with the ability to make very fine pitch interconnects not feasible with solder, avoidance of lead (Pb), certain desirable electrical and mechanical properties, and simpler and lower temperature processing. The principal concerns with ACF are its long-term reliability and stability, and consistent electrical performance of the particulate interconnects. In this paper, results of rigorous process development and reliability testing using a set of test vehicles covering both CSP and PBGA package formats are discussed and analyzed. Two different low-cost bump structures on the die side and a few different substrate materials and designs were investigated. Since the application of the ACF material and thermo-compression attachment of the chip are two unique steps in the package assembly process, extensive design of experiments (DOE) was performed. Developmental reliability testing was done to gain insight into the failure mechanisms of these type of interconnects. Systematic refinements in the assembly process, the material choice and design rules for the die and substrates were made based on the understanding developed from these investigations.

A new flip chip packaging technology for the mid-range application space

A new flip chip packaging technology is developed which entails fine pitch bumping and assembly of standard die with perimeter bonding pads. The technology provides compelling advantages for the packaging of ICs in the mid range application space (up to /spl sim/700 pins) represented by devices such as ASICs, graphics processors, DSPs, RF/analog and others. The flip chip interconnection is accomplished by the use of gold stud bumps on the die, attached by thermocompression bonding to low-cost substrates with predispensed non-conductive adhesive (NCA) in lieu of conventional underfilling. In this paper, the structure, assembly process and reliability data of the package are presented. High levels of component level reliability are demonstrated, previously believed to be unfeasible with similar package structures. Extension of the interconnect technology to finer pitch and higher pin counts (50 /spl mu/m pitch/1000 I/O) is discussed. Finally, the electrical design and routing methodology that simplifies the structure and layer count of the substrate over comparable area array solder bump substrate designs is presented.