Pandi C. Marimuthu

Fabrication and packaging of microbump interconnections for 3D TSV

Memory bandwidth has become a bottleneck to processor performance for tera-scale computing needs. To reduce this obstacle, a revolution in package technologies is required for tera-scale computing requirements. 3D TSV (Through Silicon Via) stacking is believed to be one of the technologies that can meet those requirements. In advanced 3D stacking technologies, one of the important steps is to develop and assemble fine pitch, high density solder microbumps. This type of solder microbump in flip chip interconnection provides a high wiring density in silicon die with a high-performance signal and power connection. There is a growing interest in the development and study of this new type of chip stacking and bonding approach for both existing and future devices. This paper will highlight the developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies. A Cu/SnAg solder microbump with 50/40 µm in pitch was fabricated at the silicon wafer level by an electroplating method. The total thickness of the plated Cu and SnAg microbump was 20um. The under bump metallurgy (UBM) layer on the Si carrier used thin film based metal layers. The assembly of the Si chip and the Si carrier was conducted with the thermocompression flip chip bonder at different temperatures, times and pressures and the optimized bonding conditions were obtained. After assembly, the underfill process was carried out to fill the gap and achieve a void free underfilling using a material with a fine filler size. Finally, various reliability tests were carried out for mechanical characterization of microbump interconnections.

Next generation eWLB (embedded wafer level BGA) packaging

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for Fan-In WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. In this paper, there will be discussion of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging and 3D SIP. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.

Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging

With great demand of high-end applications such as high-integration microelectronics, system-in-packaging (SiP), power application and flexible ICs, a device wafer needs to be thinned down and further structured, for example, fabrication of through-silicon via for the improved performance. Therefore, handling of ultrathin wafer (less than 100¿m in thickness) becomes a great challenge for both front-end and back-end processes. In current practice, a supportive carrier substrate inclusive of silicon, ceramic, glass and tape is used to protect the thinned device wafer from cracking and deforming and make front-end, assembly and test easier to process. The materials used for bonding the device wafer onto the above mentioned substrates play a critical role in the fabrication of ultrathin devices and high-performance packages. This paper covers two parts: temporary bonding of a device wafer onto a carrier wafer and debonding after completion of the entire through-silicon-via (TSV) process. The purpose of temporary bonding is to attach the device wafer onto the rigid carrier substrate prior to the back-grinding and subsequent processes and thus prevent cracking and chipping of thinned device wafer. The temporary bonding agent allows the release of the device wafer using different approaches such as heat, UV and solvent, etc. The bonding defects such as delamination, bubbling, thickness variation and chemical attack are discussed. Much endeavor is put onto the temporary bonding materials and process optimization. Two types of temporary bonding adhesives are studied to bond a device wafer onto a glass wafer.

Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology

Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of ICs, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.

Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of wafer level, thin POP (Package on Package), and TSV (Through Silicon Via)/Interposer packaging solutions. It is expected to see more exciting interconnect technologies of wafer level packaging such as TSV, 2.5D Interposers, eWLB (embedded Wafer Level Ball Grid Array)/FO-WLP (Fan Out Wafer Level Package) to meet these needs. FO-WLP/eWLB has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. eWLB technologies are leading the way to the next level of thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple-die in very reliable, low-profile/low-warpage 2.5D and 3D solutions. The use of these embedded FO-WLP packages in a side-by-side configuration to replace a stacked package configuration, and to utilize as the base for a 3D TSV configuration, is critical to enable a more cost effective mobile market capability. Combining the analog and memory device with digital device packaging capability can provide an optimum solution for achieving the best performance in thin multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards packaging technologies with extended-die/fanout flipchip technology. Package and substrate design study, mechanical and thermal characterization of flipchip eWLB solution over high-end flipchip would be presented.

Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging

Integrated Circuits fabricated on silicon are assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demand for these electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in component level and board level reliability of next generation eWLB technologies including multi-RDL, thin eWLB, extra large eWLB with multi-chip. Standard JEDEC tests were carried out to investigate component level reliability and both failure analysis was performed to investigate potential structural defects. Daisychain eWLBs were assembled with different package size and different configuration as like thin or multi-RDL or multi-die. Test vehicles were also tested for drop and TCoB (Temperature on Board) reliability in industry standard test conditions. Next generation test vehicles passed both drop and TCoB tests. There was more than 50% improvement of characteristic lifetime with thinned eWLB in TCoB test because of its enhanced flexibility of package. This paper also presents study of package warpage behavior with temperature profile which is important for understanding of mechanical behavior of next generation 3D eWLBs.

Development of Super Thin TSV PoP

One of the hottest topics in the semiconductor industry today is a 3D packaging using Through Silicon Via (TSV) technology. Driven by the need for improved electrical performance or the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. 3D TSV interposer is an efficient and practical approach to solving die integration challenges. Many microsystem devices that will have to move to wafer-level packages will also facilitate further integration using silicon TSV interposers. This paper will address TSV interposer development for mobile applications to replace normal organic laminate substrate. Major driver of this work is for PoP thickness reduction since current organic PoP is one of the thickest components in cellular phone engine. Super Thin PoP test vehicle was designed in order to prove the viability of this technology. This test vehicle was a 12×12mm package with 0.4mm ball pitch on the bottom and 0.4mm pitch between the top and bottom PoP package. Test vehicle has 0.1mm thick TSV substrate and bare-die flip-chip, achieving 0.7mm total stackup height vs. equivalent organic PoP of ∼1.5mm. This paper will highlight the TSV interposer test vehicle design, fabrication, assembly process development, warpage behavior study with simulation and experimentals, component level reliability test results of the Super Thin PoP test vehicle and future steps.

Cost effective 300mm large scale eWLB (embedded Wafer Level BGA) technology

This paper will highlight some of the recent advancements in 300mm eWLB wafer development. Compared to 200mm case, 300mm eWLB wafer has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100∼150% more warpage with 300mm eWLB wafer compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper also presents study of process optimization for 300mm eWLB and on overall warpage behavior in different process steps. Finally 300mm eWLB test vehicles are fabricated and tested in JEDEC standard test conditions. It also describes mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps.

2.5D/3D TSV processes development and assembly/packaging technology

Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies.