Hyung-Ock Kim

Illuminating gravitational waves: A concordant picture of photons from a neutron star merger

GROWTH observations of GW170817 The gravitational wave event GW170817 was caused by the merger of two neutron stars (see the Introduction by Smith). In three papers, teams associated with the GROWTH (Global Relay of Observatories Watching Transients Happen) project present their observations of the event at wavelengths from x-rays to radio waves. Evans et al. used space telescopes to detect GW170817 in the ultraviolet and place limits on its x-ray flux, showing that the merger generated a hot explosion known as a blue kilonova. Hallinan et al. describe radio emissions generated as the explosion slammed into the surrounding gas within the host galaxy. Kasliwal et al. present additional observations in the optical and infrared and formulate a model for the event involving a cocoon of material expanding at close to the speed of light, matching the data at all observed wavelengths. Science, this issue p. 1565, p. 1579, p. 1559; see also p. 1554 Observations of a binary neutron star merger at multiple wavelengths can be explained by an off-axis relativistic cocoon model. Merging neutron stars offer an excellent laboratory for simultaneously studying strong-field gravity and matter in extreme environments. We establish the physical association of an electromagnetic counterpart (EM170817) with gravitational waves (GW170817) detected from merging neutron stars. By synthesizing a panchromatic data set, we demonstrate that merging neutron stars are a long-sought production site forging heavy elements by r-process nucleosynthesis. The weak gamma rays seen in EM170817 are dissimilar to classical short gamma-ray bursts with ultrarelativistic jets. Instead, we suggest that breakout of a wide-angle, mildly relativistic cocoon engulfing the jet explains the low-luminosity gamma rays, the high-luminosity ultraviolet-optical-infrared, and the delayed radio and x-ray emission. We posit that all neutron star mergers may lead to a wide-angle cocoon breakout, sometimes accompanied by a successful jet and sometimes by a choked jet.

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS

Power-gating has been widely used to reduce subthreshold leakage current. However, the extent of leakage saving through power-gating diminishes with technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-gating involves substantial increase of area and wirelength. A circuit technique called supply switching with ground collapse (SSGC) has recently been proposed to overcome the limitation of power-gating. The circuit technique is successfully applied to the register file of ARM9 microprocessor in a 1.2 V, 65-nm CMOS process, and the measured result is reported for the first time. The leakage current is reduced by a factor of 960 on average of 83 dies at 25°C , and by a factor of 150 at 85°C. Compared to a register file implemented in conventional power-gating, leakage current is cut by a factor of 2.2, demonstrating that SSGC can be a substitute for power-gating in nanometer CMOS.

Physical design methodology of power gating circuits for standard-cell-based design

The application of power gating circuits to semicustom design based on standard-cell elements is limited due to the requirement of customizing cells that are tailored for power gating or the requirement of customizing physical design methodologies for placement and power network. We propose a new power network architecture that enables use of conventional standard-cell elements. A few custom library elements are developed wherever needed, including output interface circuits and data retention storage elements. A novel method of current switch design is also described. The proposed methodology is applied to ISCAS benchmark circuits, and also to a commercial Viterbi decoder with 0.18mum CMOS technology

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65-nm and 8.6 with 45-nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from register transfer level to layout. These include the choice of standby supply voltage with circuits that support it, a power network architecture for designs based on standard-cell elements, a current switch design methodology, several circuit elements specific to the proposed scheme, and the design flow that encompasses all the components. The proposed design flow is demonstrated on a commercial design with 90-nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.

Analysis and optimization of gate leakage current of power gating circuits

Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling down of gate oxide. We try to understand the sources of leakage current in power gating circuits and show that input MOSFETs plays a crucial role in determining total gate leakage current. It is also shown that the choice of a current switch in terms of polarity, threshold voltage, and size has a significant impact on total leakage current. From the observation of the importance of input MOSFETs, we propose the power optimization of power gating circuits through input control

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements

Zigzag power gating (ZPG) can overcome the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. We propose a design framework for cell-based semicustom design of ZPG circuits, using a new power network architecture that allows the unmodified conventional logic cells to be combined with custom circuitry such as ZPG flip-flops, input forcing circuits, and current switches. The design flow, from register transfer level description to layout, is described and applied to a 32-b microprocessor design using a 1.2-V 65-nm triple-well bulk CMOS process. The use of a sleep vector in ZPG requires additional switching power when entering standby mode and returning to active mode. The switching power should be minimized so that is does not outweigh the leakage saved by employing ZPG scheme. We formulate the selection of a sleep vector as a multiobjective optimization problem, minimizing both the transition energy and the total wirelength of a design. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show an average saving of 39% in transition energy and 8% in total wirelength for several benchmark circuits in 65-nm technology.

Analysis of power consumption in VLSI global interconnects

The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. We study the trends of interconnect power consumption based on current and future technology node parameters. We show that 20%-30% of the power is consumed by interconnect resistance in optimally buffered global interconnect systems. We also study the analysis method based on a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is addressed. The theoretical results can be used for any kind of linear circuit, including RLC circuits.

Early-life-failure detection using SAT-based ATPG

Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs. Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability. Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely. In this paper, we present an automatic test pattern generation (ATPG) technique based on Boolean Satisfiability (SAT) for detecting ELF-induced delay changes at all gates in a given circuit. Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection. We also demonstrate the robustness of our approach to manufacturing process variations.

Thermal-aware body bias modulation for high performance mobile core

Thermal management, which dynamically throttles frequency and voltage, is de facto standard in high performance mobile SoC to sustain device surface temperature under specific level; and throttling must accompany with computation slowdown. To minimize performance loss, we present a new thermal management by using adaptive body bias which efficiently modulates speed and leakage current. The key problem is to optimize body voltage respect to performance as well as power in chip-to-chip process variation. We also propose a semicustom design flow with standard cells and commercial EDA tools for seamless adoption to commercial products. With the proposed method, we can reduce 12.3% of the quality loss caused by thermal management in a mobile SoC test vehicle. This is the first study and commercial use in thermal management at the best of our knowledge.