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Dive into the research topics where Kyung-woo Nam is active.

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Featured researches published by Kyung-woo Nam.


asian solid state circuits conference | 2007

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

Kyung-woo Nam; Jung-Sik Kim; Chi Sung Oh; Han-Gu Sohn; Dong-Hyuk Lee; Chang-Ho Lee; Soo-Young Kim; Jong-Wook Park; Yong-Jun Kim; Mi-Jo Kim; Jinkuk Kim; Ho-Cheol Lee; Jin-Hyoung Kwon; Dong Il Seo; Young-Hyun Jun; Kinam Kim

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.


international solid-state circuits conference | 2016

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Kyo-Min Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; Kyung-woo Nam; Seouk-Kyu Choi; Jae-Wook Lee; Uk-Song Kang; Young-Soo Sohn; Jung-Hwan Choi; Chi-wook Kim; Seong-Jin Jang; Gyo-Young Jin

Demand for higher bandwidth DRAM continues to increase, especially in high-performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.


Archive | 2007

Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof

Chi-Sung Oh; Yong-Jun Kim; Kyung-woo Nam; Jinkuk Kim; Soo-Young Kim


Archive | 2003

Refresh control circuit and methods of operation and control of the refresh control circuit

Hyun-Suk Lee; Kyung-woo Nam


Archive | 2005

Microprocessor system with memory device including a DMAC, and a bus for DMA transfer of data between memory devices

Si-Young Kim; Kyung-woo Nam; Myung-Gyoo Won; Yunsoo Lee; Jong-Won Lee; Yang-Hoon Jung


Archive | 2002

Refresh control circuit for controlling refresh cycles according to values stored in a register and related refreshing method

Kyung-woo Nam


Archive | 2007

Method, device, and system for preventing refresh starvation in shared memory bank

Dong-Hyuk Lee; Kyung-woo Nam; Yong-Jun Kim; Jong-Wook Park; Chi-Sung Oh


Archive | 2005

Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices

Kyung-woo Nam


Archive | 2009

MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD

Jin-Hyoung Kwon; Kyung-woo Nam; Han-Gu Sohn; Ho-Cheol Lee; Kwang-Myeong Jang


Archive | 2006

Semiconductor memory device capable of selectively refreshing word lines

Kyung-woo Nam

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