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Dive into the research topics where Jin-Hyoung Kwon is active.

Publication


Featured researches published by Jin-Hyoung Kwon.


symposium on vlsi technology | 2005

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

Jung-Geun Kim; D.S. Woo; Hansu Oh; H.J. Kim; Sung-Gi Kim; Byung-lyul Park; Jin-Hyoung Kwon; Myoungseob Shim; G.W. Ha; Jai-Hyuk Song; N.J. Kang; J.M. Park; Ho Kyong Hwang; S.S. Song; Young-Nam Hwang; Dae-youn Kim; D. H. Kim; M. Huh; D.H. Han; C.S. Lee; Seok-Han Park; Yongho Kim; Y.S. Lee; Min-wook Jung; Young-Ran Kim; B.H. Lee; Myung-Haing Cho; W.T. Choi; Hyun-Su Kim; G.Y. Jin

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.


asian solid state circuits conference | 2007

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

Kyung-woo Nam; Jung-Sik Kim; Chi Sung Oh; Han-Gu Sohn; Dong-Hyuk Lee; Chang-Ho Lee; Soo-Young Kim; Jong-Wook Park; Yong-Jun Kim; Mi-Jo Kim; Jinkuk Kim; Ho-Cheol Lee; Jin-Hyoung Kwon; Dong Il Seo; Young-Hyun Jun; Kinam Kim

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.


symposium on vlsi technology | 2004

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

J.M. Park; Young-Nam Hwang; Dong-woon Shin; M. Huh; D. H. Kim; Ho Kyong Hwang; Hansu Oh; Jai-Hyuk Song; N.J. Kang; B.H. Lee; C.J. Yun; Myoungseob Shim; Sung-Gi Kim; Jung-Geun Kim; Jin-Hyoung Kwon; Byung-lyul Park; J.W. Lee; Dae-youn Kim; Myoung-kwan Cho; M.Y. Jeong; H.J. Kim; Hyun-Su Kim; G.Y. Jin; Yeonsang Park; Kinam Kim

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).


Archive | 2008

MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE

Jin-Hyoung Kwon; Han-Gu Sohn; Dong-Woo Lee


Archive | 2011

Multiprocessor system comprising multi-port semiconductor memory device

Jin-Hyoung Kwon


Archive | 2008

Multiport semiconductor memory device having protocol-defined area and method of accessing the same

Jin-Hyoung Kwon; Han-Gu Sohn; Kwang-Myeong Jang


Archive | 2008

Memory system and method with flash memory device

Sung-Kyu Jo; Jin-Hyoung Kwon


Archive | 2009

MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD

Jin-Hyoung Kwon; Kyung-woo Nam; Han-Gu Sohn; Ho-Cheol Lee; Kwang-Myeong Jang


Archive | 2008

SEMICONDUCTOR MEMORY DEVICE HAVING PROCESSOR RESET FUNCTION AND RESET CONTROL METHOD THEREOF

Jin-Hyoung Kwon; Han-Gu Sohn


Archive | 2010

Multiprocessor system having multiport semiconductor memory device and nonvolatile memory with shared bus

Jin-Hyoung Kwon

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