L. A. Almeida

Improved morphology and crystalline quality of MBE CdZnTe/Si

We report on continuing efforts to develop a reproducible process for molecular beam epitaxy of CdZnTe on three-inch, (211) Si wafers. Through a systematic study of growth parameters, we have significantly improved the crystalline quality and have reduced the density of typical surface defects. Lower substrate growth temperatures (∼250–280°C) and higher CdZnTe growth rates improved the surface morphology of the epilayers by reducing the density of triangular surface defects. Cyclic thermal annealing was found to reduce the dislocation density. Epilayers were characterized using Nomarski microscopy, scanning electron microscopy, x-ray diffraction, defect-decoration etching, and by their use as substrates for HgCdTe epitaxy.

Characterization of cross-hatch morphology of MBE (211) HgCdTe

We present the results of a detailed study of the nature and origin of cross-hatch patterns commonly observed on (211) HgCdTe epilayers deposited by molecular beam epitaxy. Cross-hatch patterns were examined using x-ray topography as well as Nomarski, interferometric, and atomic force microscopies. Cross-hatch patterns were generally comprised of three sets of lines, parallel to the [231],, [213], and [011] directions. The lines parallel to the [011] direction exhibited distinct properties compared to the two sets of lines parallel to [231] and [213]. Under growth conditions characterized by excessive Hg flux (low temperature), lines parallel to [011] were periodic and tended to dominate the cross-hatch pattern. In some cases, bands of dislocations, 10–100 m in width, formed parallel to [011]. Under optimized growth conditions, on very closely lattice-matched substrates, (dislocation densities <105 cm−2) lines parallel to [011] vanished entirely, and lines parallel to [231] and [213] became sparse. The remaining lines were typically fragments terminated by either a single dislocation, a cluster of dislocations (micro-void), or the wafers edge. The density of these line fragments tended to decrease as the dislocation density decreased. Under the best growth conditions on very closely lattice-matched substrates we have achieved dislocation densities of 5 104 cm−2, which is comparable to the dislocation density of the CdZnTe substrate.

Impact of Tellurium Precipitates in CdZnTe Substrates on MBE HgCdTe Deposition

State-of-the-art (112)B CdZnTe substrates were examined for near-surface tellurium precipitate-related defects. The Te precipitate density was observed to be fairly uniform throughout the bulk of the wafer, including the near-surface region. After a molecular beam epitaxy (MBE) preparation etch, exposed Te precipitates, small pits, and bumps on the (112)B surface of the CdZnTe wafer were observed. From near-infrared and dark field microscopy, the bumps and small pits on the CdZnTe surface are associated with strings of Te precipitates. Raised bumps are Te precipitates near the surface of the (112)B CdZnTe where the MBE preparation etch has not yet exposed the Te precipitate(s). An exposed Te precipitate sticking above the etched CdZnTe surface plane occurs when the MBE preparation etch rapidly undercuts a Te precipitate. Shallow surface pits are formed when the Te precipitate is completely undercut from the surrounding (112)B surface plane. The Te precipitate that was previously located at the center of the pit is liberated by the MBE preparation etch process.

Influence of photoresist feature geometry on ECR plasma-etched HgCdTe trenches

Factors that affect width and aspect ratio in electron cyclotron resonance (ECR) etched HgCdTe trenches are investigated. The ECR etch bias and anisotropy are determined by photoresist feature erosion rate. The physical characteristics of the trenches are attributed to ECR plasma etch chemistry.

A Review of the Characterization Techniques for the Analysis of Etch Processed Surfaces of HgCdTe and Related Compounds

HgCdTe is the material system of choice for many infrared sensing applications. Growth of this material can often be challenging. However, processing of this material system can be equally as challenging. Incorrect processing can cause shunting, surface inversion, or high surface recombination velocities that can be detrimental. In order to produce an effective device in HgCdTe, one needs to understand what happens to the HgCdTe surface. Factors like the chemical termination of the HgCdTe surface, surface roughness, and surface reconstruction after a process is performed can dramatically affect the performance of devices made with HgCdTe. We will review different surface characterization techniques and how these techniques can be used conventionally and unconventionally, and how different processes can affect the surfaces of HgCdTe and related compounds.

Understanding the Evolution of CdTe Buffer Layer Surfaces on ZnTe/Si(211) and GaAs(211)B During Cyclic Annealing

We present the results of a detailed study of the changes that occur on CdTe buffer layer surfaces grown on ZnTe/Si(211) and GaAs(211)B during the routine thermal cyclic annealing (TCA) process. Observations indicate that CdTe buffer layer surfaces are Te saturated when the TCA is performed under Te overpressure. In the absence of Te flux during the TCA step, the CdTe surface loses CdTe congruently and the typical CdTe nanowires show the presence of nodules on their surfaces. The observed changes in reflection high-energy electron diffraction patterns during TCA are explained in terms of surface chemistry and topography observations. Overall, the Te overpressure is necessary to maintain a smoother and pristine surface to continue the molecular beam epitaxy (MBE) growth.

Analysis of Mesa Dislocation Gettering in HgCdTe/CdTe/Si(211) by Scanning Transmission Electron Microscopy

Due to its strong infrared absorption and variable band-gap, HgCdTe is the ideal detector material for high-performance infrared focal-plane arrays (IRFPAs). Next-generation IRFPAs will utilize dual-color high-definition formats on large-area substrates such as Si or GaAs. However, heteroepitaxial growth on these substrates is plagued by high densities of lattice-mismatch-induced threading dislocations (TDs) that ultimately reduce IRFPA operability. Previously we demonstrated a postgrowth technique with the potential to eliminate or move TDs such that they have less impact on detector operability. In this technique, highly reticulated mesa structures are produced in as-grown HgCdTe epilayers, and then subjected to thermal cycle annealing. To fully exploit this technique, better understanding of the inherent mechanism is required. In this work, we employ scanning transmission electron microscopy (STEM) analysis of HgCdTe/CdTe/Si(211) samples prepared by focused ion beam milling. A key factor is the use of defect-decorated samples, which allows for a correlation of etch pits observed on the surface with underlying dislocation segments viewed in cross-section STEM images. We perform an analysis of these dislocations in terms of the general distribution, density, and mobility at various locations within the mesa structures. Based on our observations, we suggest factors that contribute to the underlying mechanism for dislocation gettering.

Impurity Gettering in (112)B HgCdTe/CdTe/Alternate Substrates

The crystalline structure and impurity profiles of HgCdTe/CdTe/alternate substrate (AS; Si and GaAs are possibilities) and CdTe/AS were analyzed by secondary-ion mass spectrometry, atomic force microscopy, etch pit density analysis, and scanning transmission electron microscopy. Impurities (Li, Na, and K) were shown to getter in as-grown CdTe/Si epilayers at in situ Te-stabilized thermal anneal (~500°C) interfaces. In HgCdTe/CdTe/Si epilayers, indium accumulation was observed at Te-stabilized thermal anneal interfaces. Impurity accumulation was measured at HgCdTe/CdTe and CdTe/ZnTe interfaces. Processing anneals were found to nearly eliminate the gettering effect at the in situ Te-stabilized thermal anneal interfaces. Impurities were found to redistribute to the front HgCdTe/CdTe/Si surface and p–n junction interfaces during annealing steps. We also investigated altering the in situ Te-stabilized thermal anneal process to enhance the gettering effect.