L. Filipovic

On the validity of momentum relaxation time in low-dimensional carrier gases

The momentum relaxation time (MRT) is widely used to simplify low-field mobility calculations including anisotropic scattering processes. Although not always fully justified, it has been very practical in simulating transport in bulk and in low-dimensional carrier gases alike. We review the assumptions behind the MRT, quantify the error introduced by its usage for low-dimensional carrier gases, and point out its weakness in accounting for inter-subband interaction, occurring specifically at low inversion densities.

Synthesis, Morphological, and Electro-optical Characterizations of Metal/Semiconductor Nanowire Heterostructures

In this letter, we demonstrate the formation of unique Ga/GaAs/Si nanowire heterostructures, which were successfully implemented in nanoscale light-emitting devices with visible room temperature electroluminescence. Based on our recent approach for the integration of InAs/Si heterostructures into Si nanowires by ion implantation and flash lamp annealing, we developed a routine that has proven to be suitable for the monolithic integration of GaAs nanocrystallite segments into the core of silicon nanowires. The formation of a Ga segment adjacent to longer GaAs nanocrystallites resulted in Schottky-diode-like I/V characteristics with distinct electroluminescence originating from the GaAs nanocrystallite for the nanowire device operated in the reverse breakdown regime. The observed electroluminescence was ascribed to radiative band-to-band recombinations resulting in distinct emission peaks and a low contribution due to intraband transition, which were also observed under forward bias. Simulations of the obtained nanowire heterostructure confirmed the proposed impact ionization process responsible for hot carrier luminescence. This approach may enable a new route for on-chip photonic devices used for light emission or detection purposes.

Effects of sidewall scallops on open tungsten TSVs

In order to examine the effects of sidewall scallops on through-silicon via (TSV) performance, the etch processes required to generate several TSV geometries are simulated and the resulting structures are imported into a finite element tool for electrical parameter extraction and reliability analysis. The electrical models, which were confirmed using experimental measurements with non-scalloped structures, are applied to the simulated TSV devices. The effects of the scalloped features are investigated by comparing the performance of a TSV with scalloped sidewalls to one with flat walls. In addition, the variation in TSV performance, when the sidewall scallop height is varied, is analyzed. A link between increased scallop height and increased resistance and signal loss is observed. The maximum thermo-mechanical stress in the structure is also noted to increase with the presence of large scallops, but the overall average stress does not vary significantly.

Impact of across-wafer variation on the electrical performance of TSVs

A simulation methodology is presented by which measured equipment variation during silicon DRIE is quantified and the effective variation in the electrical performance of the final TSV devices is found. Using the level set method, process simulations are performed in order to generate structures representative of the equipment variation. The across-wafer variation of the resulting scallop geometry is about 20%, while the electrical performance, including the resistance, capacitance, and inductance of the devices was found to not vary beyond 1%.

Full-band transport in ultra-narrow p-type Si channels: Field, orientation, strain

We present a framework for modeling the low-field mobility of ultra-narrow Si channels such as nanowires or FinFETs based on a full-band description of the electronic structure. Hole mobility is of particular interest since its calculation necessitates a full-band approach. Using cylindrical nanowires of different crystal orientation as a model for an ultra-narrow channel, we investigate the transport distribution and demonstrate the effects of orientation, bias, and strain on the mobility.

Investigation of quantum transport in nanoscaled GaN high electron mobility transistors

In this paper, a comprehensive investigation of quantum transport in nanoscaled gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A simulation model for quantum transport in nanodevices on unstructured grids in arbitrary dimension and for arbitrary crystal directions has been developed. The model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method. A new approach to reduce its computational effort has been realized. The model has been used to achieve a consistent treatment of quantization and transport effects in deeply scaled asymmetric GaN HEMTs. The self-consistent electron concentration, conduction band edges and ballistic current have been calculated. The effects of strain relaxation at the heterostructure interfaces on the potential and carrier concentration have been shown.

Advanced Numerical Methods for Semi-classical Transport Simulation in Ultra-Narrow Channels

In this work we present a semi-classical modeling and simulation approach for ultra-narrow channels that has been implemented as part of the Vienna Schrodinger-Poisson (VSP) simulation framework (Baumgartner, J Comput Electron 12:701–721, 2013; http://www.globaltcad.com/en/products/vsp.html (2014)) over the past few years. Our research has been driven by two goals: maintaining high physical accuracy of the models while producing a computationally efficient and flexible simulation code.

Modeling electromigration in nanoscaled copper interconnects

In this work we present an approach to modeling grain boundaries and material interfaces in nanoscaled copper interconnects. Using a sample structure with a 40nm×40nm cross section and an applied current density of 1MA/cm2, we perform a comparative analysis while ignoring or including grains, with an average grain size of 50nm. The novelty in our approach is the treatment of microstructure interfaces using a binary parameter, which is further used to define interface-specific material properties for copper resistivity and electromigration modeling. Our models show that the inclusion of microstructure effects results in an increased resistance, increased vacancy migration, and ultimately in a higher EM-induced stress.

Band-to-band tunneling in 3D devices

This work focuses on studying band-to-band tunneling in 3D devices, while considering variations in material properties (mass, doping), applied bias, or geometry. A simulation study of cylindrical nanowires, tapered structures and doping concentration variation demonstrates the importance of 3D effects in band-to-band tunneling current computation.

Fast methods for full-band mobility calculation

Accurate band structure modeling is an essential ingredient in mobility modeling for any kind of semiconductor device or channel. This is particularly true for holes as the valence band of the most commonly used semiconductor materials is not even close to being parabolic. Instead, valence bands exhibit warped energy surfaces that simply cannot be approximated with parabolic valleys. To make matters worse, nanostructured channels can have large quantization energies resulting in complex, highly orientation-dependent kinetic behavior of both holes and electrons. In this work, we present an accurate and computationally efficient method for calculating channel low-feld mobilities based on a numeric band structure from a k·p model.