R. L. de Orio
Vienna University of Technology
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Featured researches published by R. L. de Orio.
Microelectronics Reliability | 2010
R. L. de Orio; H. Ceric; Siegfried Selberherr
Electromigration failure is a major reliability concern for integrated circuits. The continuous shrinking of metal line dimensions together with the interconnect structure arranged in many levels of wiring with thousands of interlevel connections, such as vias, make the metallization structure more susceptible to failure. Mathematical modeling of electromigration has become an important tool for understanding the electromigration failure mechanisms. Therefore, in this work we review several electromigration models which have been proposed over the years. Starting from the early derivation of Blacks equation, we present the development of the models in a somewhat chronological order, until the recent develop- ments for fully three-dimensional simulation models. We focus on the most well known, continuum physically based models which have been suitable for comprehensive TCAD analysis.
IEEE Transactions on Device and Materials Reliability | 2009
H. Ceric; R. L. de Orio; Johann Cervenka; Siegfried Selberherr
The demanding task of assessing long-time interconnect reliability can only be achieved by combination of experimental and technology computer-aided design (TCAD) methods. The basis for a TCAD tool is a sophisticated physical model which takes into account the microstructural characteristics of copper. In this paper, a general electromigration model is presented with special focus on the influence of grain boundaries and mechanical stress. The possible calibration and usage scenarios of electromigration tools are discussed. The physical soundness of the model is proved by 3-D simulations of typical dual-damascene structures used in accelerated electromigration testing.
Microelectronics Reliability | 2011
R. L. de Orio; H. Ceric; Siegfried Selberherr
A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.
Microelectronics Reliability | 2012
R. L. de Orio; H. Ceric; Siegfried Selberherr
Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.
international reliability physics symposium | 2014
L. Filipovic; R. L. de Orio; Siegfried Selberherr; Anderson Pires Singulani; F. Roger; R. Minixhofer
In order to examine the effects of sidewall scallops on through-silicon via (TSV) performance, the etch processes required to generate several TSV geometries are simulated and the resulting structures are imported into a finite element tool for electrical parameter extraction and reliability analysis. The electrical models, which were confirmed using experimental measurements with non-scalloped structures, are applied to the simulated TSV devices. The effects of the scalloped features are investigated by comparing the performance of a TSV with scalloped sidewalls to one with flat walls. In addition, the variation in TSV performance, when the sidewall scallop height is varied, is analyzed. A link between increased scallop height and increased resistance and signal loss is observed. The maximum thermo-mechanical stress in the structure is also noted to increase with the presence of large scallops, but the overall average stress does not vary significantly.
international integrated reliability workshop | 2014
R. L. de Orio; S. Gousseau; S. Moreau; H. Cerice; Siegfried Selberherr; A. Farcy; F. Bay; K. Inal; P. Montmitonnet
We investigate the material depletion rate from a fatal void due to electromigration in a Cu interconnect structure ended by a TSV. Experiments show the formation of a fatal void above the TSV. Its volumetric growth rate is practically constant for an extended period, but at longer times a significant increase is observed. We have carried out numerical simulations to reproduce the aforementioned void growth behavior. The model incorporates the void size dependence on the incoming flux of vacancies due to electromigration. The simulation results have provided a good description for the void volume and for the growth rate increase for the entire time window of the experiments.
international conference on simulation of semiconductor processes and devices | 2013
H. Ceric; A. Pires Singulani; R. L. de Orio; Siegfried Selberherr
Solder bumps are important interconnect components for 3D integration. Their mechanical and electrical properties influence the overall reliability of 3D ICs. A characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation influences the operation of 3D ICs and, in connection with electro-migration, may cause failures in ICs. In this paper we present a model for describing the growth of intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on the new model are discussed in conjunction with corresponding experimental findings.
international conference on simulation of semiconductor processes and devices | 2011
R. L. de Orio; H. Ceric; Siegfried Selberherr
A compact model for early electromigration failures in copper dual-damascene M1/via structures is proposed. The model is derived based on relevant physical effects of the early failure mode, where a rigorous void nucleation model and a simple mechanism for slit void growth are considered. As a result, a simple analytical model for the early electromigration lifetime is obtained. In addition, it is shown that the simulations provide a reasonable estimation for the early lifetimes.
international symposium on the physical and failure analysis of integrated circuits | 2010
H. Ceric; R. L. de Orio; Siegfried Selberherr
Modern interconnect structures are exposed to high mechanical stresses during their operation. These stresses have their sources in interconnect process technology and electromigration. The mechanical properties of passivating films and the choice of process technology influence electromigration reliability. In this paper we analyze the interplay between electromigration and mechanical stress on an atomistic level. A stress-dependent diffusion tensor has been derived and implemented in a continuum electromigration model. Since the vacancy dynamics at grain boundaries also contributes to the stress distribution, the electromigration model has been extended by a grain boundary model. The plausibility of the compound model is demonstrated with an example of stress dependent electromigration in a three-dimensional, dual-damascene interconnect structure.
international conference on simulation of semiconductor processes and devices | 2008
H. Ceric; R. L. de Orio; Johann Cervenka; Siegfried Selberherr
The standard electromigration model is extended by introducing an anisotropic diffusivity which depends on the general stress tensor and a new model of grain boundaries which describes dynamics of mobile vacancies and vacancies trapped in grain boundaries. The application scenario for electromigration simulation is presented. The new calibration and usage concept takes into account microstructural diversity of interconnect inputs. A simulation example illustrating the effect of microstructural variation is presented and discussed.