Frederic Roger

Through Silicon Via Reliability

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

Intrinsic stress analysis of tungsten-lined open TSVs

Abstract The effects of silicon etching and subsequent metallization during the fabrication of tungsten-lined open TSVs are examined using a combination of measurements and simulations. The total stress through a tungsten film deposited on a flat wafer is measured and finite element simulations are performed in order to identify the intrinsic and thermal stress components in the film. The data is then used to observe and model the stress through a TSV structure, which is etched using the DRIE process, resulting in scalloped inner sidewalls through the TSV opening. The scalloped structure is then compared to the ideal flat alternative with regard to the stress through the metal film and the TSVs electrical parameters, including resistance, capacitance, and inductance. It is found that the stress around the scallop varies significantly while the average stress through the tungsten in the flat TSV is only slightly higher than the stress observed through the scalloped structure. The resistance, capacitance, and inductance are all found to increase in the presence of scallops.

Impact of across-wafer variation on the electrical performance of TSVs

A simulation methodology is presented by which measured equipment variation during silicon DRIE is quantified and the effective variation in the electrical performance of the final TSV devices is found. Using the level set method, process simulations are performed in order to generate structures representative of the equipment variation. The across-wafer variation of the resulting scallop geometry is about 20%, while the electrical performance, including the resistance, capacitance, and inductance of the devices was found to not vary beyond 1%.

An EBIC Model for TCAD Simulation to Determine the Surface Recombination Rate in Semiconductor Devices

A 3-D electron-beam-induced current (EBIC) model was implemented in technology computer aided design simulations. The model uses a carefully designed charge carrier generation profile that describes how an electron beam induces charge carriers in a semiconducting device and then drift-diffusion equations are solved to determine the resulting current. The simulation provides a map of the EBIC signal, which can be compared with experimental 2-D profiles. This comparison can be used to fit parameters such as the surface recombination rate which is otherwise difficult to fit in completed devices. Additional experimental data for these fits are obtained by performing the experiments at different electron beam energies and thereby generating carriers at different depths in the sample. The experiments were performed on cross sections of silicon photodiodes with varying surface preparations. A strong influence of the surface preparation method on the charge carrier diffusion was observed.

Investigations on CMOS photodiodes using scanning electron microscopy with electron beam induced current measurements

In this work the characterization of CMOS diodes with Electron Beam Induced Current (EBIC) measurements in a Scanning Electron Microscope (SEM) are presented. Three-dimensional Technology Computer Aided Design (TCAD) simulations of the EBIC measurement were performed for the first time to help interpret the experimental results. The TCAD simulations provide direct access to the spatial distribution of physical quantities (like mobility, lifetime etc.) which are very difficult to obtain experimentally. For the calibration of the simulation to the experiments, special designs of vertical p-n diodes were fabricated. These structures were investigated with respect to doping concentration, beam energy, and biasing. A strong influence of the surface preparation on the measurements and the extracted diffusion lengths are shown.

TCAD study of Single Photon Avalanche Diode on 0.35μm high voltage technology

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

Optical sensor process variability in a 0.18 μm high voltage CMOS technology

We describe an analysis of the main process parameters variability involved in electrical and optical output characteristics of an optical sensor integrating a standard silicon-based NWell in p-epitaxial substrate photodiode and an UV/IR blocking interference filter. This study is done with TCAD simulation following a standard 0.18 μm high voltage CMOS technology fabrication process. The TCAD simulations combined with specific Design of Experiments permit a better understanding of the main electrical and optical responses variabilities of the optical sensor. This results in an improvement of the inline process control parameters and a better modeling of the sensor for future circuit designs integrating this sensor.

Towards probabilistic analog behavioral modeling

Analog behavioral models are widely used to reduce the complexity in hierarchical analog circuit design and verification. In the presence of process variations and atomic-level fluctuations, however, these models have to be extended to take variability into account. In this paper, we present a probabilistic solution that treats the behavioral model coefficients as multidimensional random variables and supports non-Gaussian as well as correlated parameters. A voltage divider and a bandgap voltage reference demonstrate the capabilities of our modeling approach in terms of accuracy and efficiency.

Three-dimensional simulation for the reliability and electrical performance of through-silicon vias

The electrical performance and reliability of a through-silicon via is investigated through two-dimensional and three-dimensional simulations. Due to the large differences in material thicknesses present in the structures, a 3D simulation is often not feasible. The thermo-mechanical stress, the electrical parameters including TSV resistance and capacitance, as well as the electromigration-induced stress are investigated. A comparison between the results obtained through 2D and 3D simulations is used to suggest which types of simulations require a 3D modelling approach. It is found that an appropriate analysis of the current density through the structure requires 3D simulation, meaning that electromigration phenomena must be studied with 3D simulation or at least a combination of 2D and 3D analysis. However, a 2D simulation with assumed rotational symmetry is sufficient to estimate the thermo-mechanical stress distribution through the structure as well as the parasitic capacitance and signal loss of the TSV.

A novel simulation methodology for development of ESD primitives on a 0.18µm analog, mixed-signal high voltage process technology

This paper presents a full simulation methodology dedicated to the ESD primitive devices development in High Voltage technology. This workflow based on layout generation, 2D, 3D and mixed-mode TCAD simulations and SPICE simulations provide robust devices sustaining ESD stress tests.